payloads/libpayload/drivers/serial/qcs405.c

   1 /*
   2  * Copyright (c) 2010-2012, 2014, 2016, 2019, The Linux Foundation.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above
  11  *       copyright notice, this list of conditions and the following
  12  *       disclaimer in the documentation and/or other materials provided
  13  *       with the distribution.
  14  *     * Neither the name of The Linux Foundation nor the names of its
  15  *       contributors may be used to endorse or promote products derived
  16  *       from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  19  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  25  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  26  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  27  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  28  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <libpayload.h>
  32
  33 #define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
  34
  35 enum MSM_BOOT_UART_DM_PARITY_MODE {
  36         MSM_BOOT_UART_DM_NO_PARITY,
  37         MSM_BOOT_UART_DM_ODD_PARITY,
  38         MSM_BOOT_UART_DM_EVEN_PARITY,
  39         MSM_BOOT_UART_DM_SPACE_PARITY
  40 };
  41
  42 /* UART Stop Bit Length */
  43 enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
  44         MSM_BOOT_UART_DM_SBL_9_16,
  45         MSM_BOOT_UART_DM_SBL_1,
  46         MSM_BOOT_UART_DM_SBL_1_9_16,
  47         MSM_BOOT_UART_DM_SBL_2
  48 };
  49
  50 /* UART Bits per Char */
  51 enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
  52         MSM_BOOT_UART_DM_5_BPS,
  53         MSM_BOOT_UART_DM_6_BPS,
  54         MSM_BOOT_UART_DM_7_BPS,
  55         MSM_BOOT_UART_DM_8_BPS
  56 };
  57
  58 /* 8-N-1 Configuration */
  59 #define MSM_BOOT_UART_DM_8_N_1_MODE     (MSM_BOOT_UART_DM_NO_PARITY | \
  60                                          (MSM_BOOT_UART_DM_SBL_1 << 2) | \
  61                                          (MSM_BOOT_UART_DM_8_BPS << 4))
  62
  63 /* UART_DM Registers */
  64
  65 /* UART Operational Mode Register */
  66 #define MSM_BOOT_UART_DM_MR1(base)              ((base) + 0x00)
  67 #define MSM_BOOT_UART_DM_MR2(base)              ((base) + 0x04)
  68 #define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF    (1 << 8)
  69 #define MSM_BOOT_UART_DM_LOOPBACK               (1 << 7)
  70
  71 #define PERIPH_BLK_BLSP                 1
  72
  73 /* UART Clock Selection Register */
  74 #if PERIPH_BLK_BLSP
  75 #define MSM_BOOT_UART_DM_CSR(base)              ((base) + 0xA0)
  76 #else
  77 #define MSM_BOOT_UART_DM_CSR(base)              ((base) + 0x08)
  78 #endif
  79
  80 /* UART DM TX FIFO Registers - 4 */
  81 #if PERIPH_BLK_BLSP
  82 #define MSM_BOOT_UART_DM_TF(base, x)            ((base) + 0x100+(4*(x)))
  83 #else
  84 #define MSM_BOOT_UART_DM_TF(base, x)            ((base) + 0x70+(4*(x)))
  85 #endif
  86
  87 /* UART Command Register */
  88 #if PERIPH_BLK_BLSP
  89 #define MSM_BOOT_UART_DM_CR(base)               ((base) + 0xA8)
  90 #else
  91 #define MSM_BOOT_UART_DM_CR(base)               ((base) + 0x10)
  92 #endif
  93 #define MSM_BOOT_UART_DM_CR_RX_ENABLE           (1 << 0)
  94 #define MSM_BOOT_UART_DM_CR_RX_DISABLE          (1 << 1)
  95 #define MSM_BOOT_UART_DM_CR_TX_ENABLE           (1 << 2)
  96 #define MSM_BOOT_UART_DM_CR_TX_DISABLE          (1 << 3)
  97
  98 /* UART Channel Command */
  99 #define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)       ((x & 0x0f) << 4)
 100 #define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)       ((x >> 4) << 11)
 101 #define MSM_BOOT_UART_DM_CR_CH_CMD(x)           \
 102         (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
 103 #define MSM_BOOT_UART_DM_CMD_NULL               MSM_BOOT_UART_DM_CR_CH_CMD(0)
 104 #define MSM_BOOT_UART_DM_CMD_RESET_RX           MSM_BOOT_UART_DM_CR_CH_CMD(1)
 105 #define MSM_BOOT_UART_DM_CMD_RESET_TX           MSM_BOOT_UART_DM_CR_CH_CMD(2)
 106 #define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT     MSM_BOOT_UART_DM_CR_CH_CMD(3)
 107 #define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT    MSM_BOOT_UART_DM_CR_CH_CMD(4)
 108 #define MSM_BOOT_UART_DM_CMD_START_BRK          MSM_BOOT_UART_DM_CR_CH_CMD(5)
 109 #define MSM_BOOT_UART_DM_CMD_STOP_BRK           MSM_BOOT_UART_DM_CR_CH_CMD(6)
 110 #define MSM_BOOT_UART_DM_CMD_RES_CTS_N          MSM_BOOT_UART_DM_CR_CH_CMD(7)
 111 #define MSM_BOOT_UART_DM_CMD_RES_STALE_INT      MSM_BOOT_UART_DM_CR_CH_CMD(8)
 112 #define MSM_BOOT_UART_DM_CMD_PACKET_MODE        MSM_BOOT_UART_DM_CR_CH_CMD(9)
 113 #define MSM_BOOT_UART_DM_CMD_MODE_RESET         MSM_BOOT_UART_DM_CR_CH_CMD(C)
 114 #define MSM_BOOT_UART_DM_CMD_SET_RFR_N          MSM_BOOT_UART_DM_CR_CH_CMD(D)
 115 #define MSM_BOOT_UART_DM_CMD_RES_RFR_N          MSM_BOOT_UART_DM_CR_CH_CMD(E)
 116 #define MSM_BOOT_UART_DM_CMD_RES_TX_ERR         MSM_BOOT_UART_DM_CR_CH_CMD(10)
 117 #define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE        MSM_BOOT_UART_DM_CR_CH_CMD(11)
 118 #define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT    MSM_BOOT_UART_DM_CR_CH_CMD(12)
 119 #define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT     MSM_BOOT_UART_DM_CR_CH_CMD(13)
 120 #define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT    MSM_BOOT_UART_DM_CR_CH_CMD(14)
 121
 122 /*UART General Command */
 123 #define MSM_UART_DM_CR_GENERAL_CMD(x)           ((x) << 8)
 124
 125 #define MSM_BOOT_UART_DM_GCMD_NULL              MSM_UART_DM_CR_GENERAL_CMD(0)
 126 #define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN        MSM_UART_DM_CR_GENERAL_CMD(1)
 127 #define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS       MSM_UART_DM_CR_GENERAL_CMD(2)
 128 #define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT    MSM_UART_DM_CR_GENERAL_CMD(3)
 129 #define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE    MSM_UART_DM_CR_GENERAL_CMD(4)
 130 #define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT     MSM_UART_DM_CR_GENERAL_CMD(5)
 131 #define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT     MSM_UART_DM_CR_GENERAL_CMD(6)
 132
 133 /* UART Interrupt Mask Register */
 134 #if PERIPH_BLK_BLSP
 135 #define MSM_BOOT_UART_DM_IMR(base)              ((base) + 0xB0)
 136 #else
 137 #define MSM_BOOT_UART_DM_IMR(base)              ((base) + 0x14)
 138 #endif
 139
 140 #define MSM_BOOT_UART_DM_TXLEV                  (1 << 0)
 141 #define MSM_BOOT_UART_DM_RXHUNT                 (1 << 1)
 142 #define MSM_BOOT_UART_DM_RXBRK_CHNG             (1 << 2)
 143 #define MSM_BOOT_UART_DM_RXSTALE                (1 << 3)
 144 #define MSM_BOOT_UART_DM_RXLEV                  (1 << 4)
 145 #define MSM_BOOT_UART_DM_DELTA_CTS              (1 << 5)
 146 #define MSM_BOOT_UART_DM_CURRENT_CTS            (1 << 6)
 147 #define MSM_BOOT_UART_DM_TX_READY               (1 << 7)
 148 #define MSM_BOOT_UART_DM_TX_ERROR               (1 << 8)
 149 #define MSM_BOOT_UART_DM_TX_DONE                (1 << 9)
 150 #define MSM_BOOT_UART_DM_RXBREAK_START          (1 << 10)
 151 #define MSM_BOOT_UART_DM_RXBREAK_END            (1 << 11)
 152 #define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ      (1 << 12)
 153
 154 #define MSM_BOOT_UART_DM_IMR_ENABLED    (MSM_BOOT_UART_DM_TX_READY |    \
 155                                          MSM_BOOT_UART_DM_TXLEV |       \
 156                                          MSM_BOOT_UART_DM_RXSTALE)
 157
 158 /* UART Interrupt Programming Register */
 159 #define MSM_BOOT_UART_DM_IPR(base)              ((base) + 0x18)
 160 #define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB      0x0f
 161 #define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB      0       /* Not used currently */
 162
 163 /* UART Transmit/Receive FIFO Watermark Register */
 164 #define MSM_BOOT_UART_DM_TFWR(base)             ((base) + 0x1C)
 165 /* Interrupt is generated when FIFO level is less than or equal to this value */
 166 #define MSM_BOOT_UART_DM_TFW_VALUE              0
 167
 168 #define MSM_BOOT_UART_DM_RFWR(base)             ((base) + 0x20)
 169 /*Interrupt generated when no of words in RX FIFO is greater than this value */
 170 #define MSM_BOOT_UART_DM_RFW_VALUE              0
 171
 172 /* UART Hunt Character Register */
 173 #define MSM_BOOT_UART_DM_HCR(base)              ((base) + 0x24)
 174
 175 /* Used for RX transfer initialization */
 176 #define MSM_BOOT_UART_DM_DMRX(base)             ((base) + 0x34)
 177
 178 /* Default DMRX value - any value bigger than FIFO size would be fine */
 179 #define MSM_BOOT_UART_DM_DMRX_DEF_VALUE         0x220
 180
 181 /* Register to enable IRDA function */
 182 #if PERIPH_BLK_BLSP
 183 #define MSM_BOOT_UART_DM_IRDA(base)             ((base) + 0xB8)
 184 #else
 185 #define MSM_BOOT_UART_DM_IRDA(base)             ((base) + 0x38)
 186 #endif
 187
 188 /* UART Data Mover Enable Register */
 189 #define MSM_BOOT_UART_DM_DMEN(base)             ((base) + 0x3C)
 190
 191 /* Number of characters for Transmission */
 192 #define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
 193
 194 /* UART RX FIFO Base Address */
 195 #define MSM_BOOT_UART_DM_BADR(base)             ((base) + 0x44)
 196
 197 /* UART Status Register */
 198 #if PERIPH_BLK_BLSP
 199 #define MSM_BOOT_UART_DM_SR(base)               ((base) + 0x0A4)
 200 #else
 201 #define MSM_BOOT_UART_DM_SR(base)               ((base) + 0x008)
 202 #endif
 203 #define MSM_BOOT_UART_DM_SR_RXRDY               (1 << 0)
 204 #define MSM_BOOT_UART_DM_SR_RXFULL              (1 << 1)
 205 #define MSM_BOOT_UART_DM_SR_TXRDY               (1 << 2)
 206 #define MSM_BOOT_UART_DM_SR_TXEMT               (1 << 3)
 207 #define MSM_BOOT_UART_DM_SR_UART_OVERRUN        (1 << 4)
 208 #define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR       (1 << 5)
 209 #define MSM_BOOT_UART_DM_RX_BREAK               (1 << 6)
 210 #define MSM_BOOT_UART_DM_HUNT_CHAR              (1 << 7)
 211 #define MSM_BOOT_UART_DM_RX_BRK_START_LAST      (1 << 8)
 212
 213 /* UART Receive FIFO Registers - 4 in numbers */
 214 #if PERIPH_BLK_BLSP
 215 #define MSM_BOOT_UART_DM_RF(base, x)            ((base) + 0x140 + (4*(x)))
 216 #else
 217 #define MSM_BOOT_UART_DM_RF(base, x)            ((base) + 0x70 + (4*(x)))
 218 #endif
 219
 220 /* UART Masked Interrupt Status Register */
 221 #if PERIPH_BLK_BLSP
 222 #define MSM_BOOT_UART_DM_MISR(base)             ((base) + 0xAC)
 223 #else
 224 #define MSM_BOOT_UART_DM_MISR(base)             ((base) + 0x10)
 225 #endif
 226
 227 /* UART Interrupt Status Register */
 228 #if PERIPH_BLK_BLSP
 229 #define MSM_BOOT_UART_DM_ISR(base)              ((base) + 0xB4)
 230 #else
 231 #define MSM_BOOT_UART_DM_ISR(base)              ((base) + 0x14)
 232 #endif
 233
 234 /* Number of characters received since the end of last RX transfer */
 235 #if PERIPH_BLK_BLSP
 236 #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)  ((base) + 0xBC)
 237 #else
 238 #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)  ((base) + 0x38)
 239 #endif
 240
 241 /* UART TX FIFO Status Register */
 242 #define MSM_BOOT_UART_DM_TXFS(base)             ((base) + 0x4C)
 243 #define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x)      \
 244                 MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
 245 #define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x)      \
 246                 MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
 247 #define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x)      \
 248                 MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
 249 #define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x)    \
 250                 MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
 251
 252 /* UART RX FIFO Status Register */
 253 #define MSM_BOOT_UART_DM_RXFS(base)             ((base) + 0x50)
 254 #define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x)      \
 255                 MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
 256 #define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x)      \
 257                 MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
 258 #define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x)      \
 259                 MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
 260 #define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x)    \
 261                 MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
 262
 263 /* Macros for Common Errors */
 264 #define MSM_BOOT_UART_DM_E_FAILURE              1
 265 #define MSM_BOOT_UART_DM_E_TIMEOUT              2
 266 #define MSM_BOOT_UART_DM_E_INVAL                3
 267 #define MSM_BOOT_UART_DM_E_MALLOC_FAIL          4
 268 #define MSM_BOOT_UART_DM_E_RX_NOT_READY         5
 269
 270 #define UART1_DM_BASE                           ((void *)0x078af000)
 271 #define UART2_DM_BASE                           ((void *)0x078b1000)
 272
 273 enum {
 274         BLSP1_UART1,
 275         BLSP1_UART2,
 276 };
 277
 278 #define FIFO_DATA_SIZE  4
 279
 280 struct uart_params_t {
 281         void *uart_dm_base;
 282         unsigned int blsp_uart;
 283 };
 284
 285 static struct console_input_driver consin = {
 286         .havekey = serial_havechar,
 287         .getchar = serial_getchar,
 288         .input_type = CONSOLE_INPUT_TYPE_UART,
 289 };
 290
 291 static struct console_output_driver consout = {
 292         .putchar = serial_putchar,
 293 };
 294
 295 static struct uart_params_t uart_board_param = {};
 296
 297 /**
 298  * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
 299  * @uart_dm_base: UART controller base address
 300  */
 301 static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
 302 {
 303         /* Reset receiver */
 304         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 305                 MSM_BOOT_UART_DM_CMD_RESET_RX);
 306
 307         /* Enable receiver */
 308         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 309                 MSM_BOOT_UART_DM_CR_RX_ENABLE);
 310         write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base),
 311                 MSM_BOOT_UART_DM_DMRX_DEF_VALUE);
 312
 313         /* Clear stale event */
 314         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 315                 MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
 316
 317         /* Enable stale event */
 318         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 319                 MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT);
 320
 321         return 0;
 322 }
 323
 324 static unsigned int msm_boot_uart_dm_init(void  *uart_dm_base);
 325
 326 static int valid_data = 0;
 327
 328 static unsigned int word = 0;
 329
 330 /**
 331  * msm_boot_uart_dm_read - reads a word from the RX FIFO.
 332  * @data: location where the read data is stored
 333  * @count: no of valid data in the FIFO
 334  *
 335  * Reads a word from the RX FIFO. If no data is available
 336  * returns %MSM_BOOT_UART_DM_E_RX_NOT_READY.
 337  */
 338 static unsigned int
 339 msm_boot_uart_dm_read(unsigned int *data, int *count)
 340 {
 341         static int total_rx_data = 0;
 342         static int rx_data_read = 0;
 343         void *base;
 344         uint32_t status_reg;
 345
 346         base = uart_board_param.uart_dm_base;
 347
 348         if (data == NULL)
 349                 return MSM_BOOT_UART_DM_E_INVAL;
 350
 351         status_reg = read32(MSM_BOOT_UART_DM_MISR(base));
 352
 353         /* Check for DM_RXSTALE for RX transfer to finish */
 354         while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
 355                 status_reg = read32(MSM_BOOT_UART_DM_MISR(base));
 356                 return MSM_BOOT_UART_DM_E_RX_NOT_READY;
 357         }
 358
 359         /* Check for Overrun error. We'll just reset Error Status */
 360         if (read32(MSM_BOOT_UART_DM_SR(base)) &
 361                         MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
 362                 write32(MSM_BOOT_UART_DM_CR(base),
 363                         MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
 364                 total_rx_data = rx_data_read = 0;
 365                 msm_boot_uart_dm_init(base);
 366                 return MSM_BOOT_UART_DM_E_RX_NOT_READY;
 367         }
 368
 369         /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
 370         if (total_rx_data == 0)
 371                 total_rx_data =  read32(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
 372
 373         /* Data available in FIFO; read a word. */
 374         *data = read32(MSM_BOOT_UART_DM_RF(base, 0));
 375
 376         /* increment the total count of chars we've read so far */
 377         rx_data_read += FIFO_DATA_SIZE;
 378
 379         /* actual count of valid data in word */
 380         *count = ((total_rx_data < rx_data_read) ?
 381                         (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
 382                         FIFO_DATA_SIZE);
 383
 384         /* If there are still data left in FIFO we'll read them before
 385          * initializing RX Transfer again
 386          */
 387         if (rx_data_read < total_rx_data)
 388                 return 0;
 389
 390         msm_boot_uart_dm_init_rx_transfer(base);
 391         total_rx_data = rx_data_read = 0;
 392
 393         return 0;
 394 }
 395
 396 void serial_putchar(unsigned int data)
 397 {
 398         int num_of_chars = 1;
 399         void *base = uart_board_param.uart_dm_base;
 400
 401         if (data == '\n') {
 402                 num_of_chars++;
 403                 data = (data << 8) | '\r';
 404         }
 405
 406         /* Wait until transmit FIFO is empty. */
 407         while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
 408                  MSM_BOOT_UART_DM_SR_TXEMT))
 409                 udelay(1);
 410         /*
 411          * TX FIFO is ready to accept new character(s). First write number of
 412          * characters to be transmitted.
 413          */
 414         write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
 415
 416         /* And now write the character(s) */
 417         write32(MSM_BOOT_UART_DM_TF(base, 0), data);
 418 }
 419
 420 /*
 421  * msm_boot_uart_dm_reset - resets UART controller
 422  * @base: UART controller base address
 423  */
 424 static unsigned int msm_boot_uart_dm_reset(void *base)
 425 {
 426         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX);
 427         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX);
 428         write32(MSM_BOOT_UART_DM_CR(base),
 429                 MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
 430         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR);
 431         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
 432
 433         return 0;
 434 }
 435
 436 /*
 437  * msm_boot_uart_dm_init - Initializes UART controller
 438  * @uart_dm_base: UART controller base address
 439  */
 440 unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
 441 {
 442         /* Configure UART mode registers MR1 and MR2 */
 443         /* Hardware flow control isn't supported */
 444         write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0);
 445
 446         /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
 447         write32(MSM_BOOT_UART_DM_MR2(uart_dm_base),
 448                 MSM_BOOT_UART_DM_8_N_1_MODE);
 449
 450         /* Configure Interrupt Mask register IMR */
 451         write32(MSM_BOOT_UART_DM_IMR(uart_dm_base),
 452                 MSM_BOOT_UART_DM_IMR_ENABLED);
 453
 454         /*
 455          * Configure Tx and Rx watermarks configuration registers
 456          * TX watermark value is set to 0 - interrupt is generated when
 457          * FIFO level is less than or equal to 0
 458          */
 459         write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base),
 460                 MSM_BOOT_UART_DM_TFW_VALUE);
 461
 462         /* RX watermark value */
 463         write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base),
 464                 MSM_BOOT_UART_DM_RFW_VALUE);
 465
 466         /* Configure Interrupt Programming Register */
 467         /* Set initial Stale timeout value */
 468         write32(MSM_BOOT_UART_DM_IPR(uart_dm_base),
 469                 MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB);
 470
 471         /* Configure IRDA if required */
 472         /* Disabling IRDA mode */
 473         write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0);
 474
 475         /* Configure hunt character value in HCR register */
 476         /* Keep it in reset state */
 477         write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0);
 478
 479         /*
 480          * Configure Rx FIFO base address
 481          * Both TX/RX shares same SRAM and default is half-n-half.
 482          * Sticking with default value now.
 483          * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
 484          * We have found RAM_ADDR_WIDTH = 0x7f
 485          */
 486
 487         /* Issue soft reset command */
 488         msm_boot_uart_dm_reset(uart_dm_base);
 489
 490         /* Enable/Disable Rx/Tx DM interfaces */
 491         /* Data Mover not currently utilized. */
 492         write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0);
 493
 494         /* Enable transmitter */
 495         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 496                 MSM_BOOT_UART_DM_CR_TX_ENABLE);
 497
 498         /* Initialize Receive Path */
 499         msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
 500
 501         return 0;
 502 }
 503
 504 /**
 505  * serial_havechar - checks if data available for reading
 506  *
 507  * Returns 1 if data available, 0 otherwise
 508  */
 509 int serial_havechar(void)
 510 {
 511         /* Return if data is already read */
 512         if (valid_data)
 513                 return 1;
 514
 515         /* Read data from the FIFO */
 516         if (msm_boot_uart_dm_read(&word, &valid_data) != 0)
 517                 return 0;
 518
 519         return 1;
 520 }
 521
 522 /**
 523  * qcs405_serial_getc - reads a character
 524  *
 525  * Returns the character read from serial port.
 526  */
 527 int serial_getchar(void)
 528 {
 529         uint8_t byte;
 530
 531         while (!serial_havechar())
 532                 ;       /* wait for incoming data */
 533
 534         byte = (uint8_t)(word & 0xff);
 535         word = word >> 8;
 536         valid_data--;
 537
 538         return byte;
 539 }
 540
 541 /* For simplicity's sake, let's rely on coreboot initializing the UART. */
 542 void serial_console_init(void)
 543 {
 544         struct cb_serial *sc_ptr = phys_to_virt(lib_sysinfo.cb_serial);
 545
 546         if (!lib_sysinfo.cb_serial)
 547                 return;
 548
 549         uart_board_param.uart_dm_base = (void *)(uintptr_t)sc_ptr->baseaddr;
 550
 551         /* We should re-initialise uart rx as it gets reset in coreboot. */
 552         write32(MSM_BOOT_UART_DM_IMR(uart_board_param.uart_dm_base),
 553                 MSM_BOOT_UART_DM_IMR_ENABLED);
 554         msm_boot_uart_dm_init_rx_transfer(uart_board_param.uart_dm_base);
 555
 556         console_add_output_driver(&consout);
 557         console_add_input_driver(&consin);
 558 }