payloads/libpayload/drivers/usb/dwc2.c

   1 /*
   2  *
   3  * Copyright (C) 2014 Rockchip Electronics
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <libpayload.h>
  16 #include <arch/cache.h>
  17
  18 #include "dwc2.h"
  19 #include "dwc2_private.h"
  20
  21 static void dummy(hci_t *controller)
  22 {
  23 }
  24
  25 static void dwc2_reinit(hci_t *controller)
  26 {
  27         dwc2_reg_t *reg = DWC2_REG(controller);
  28         gusbcfg_t gusbcfg = { .d32 = 0 };
  29         grstctl_t grstctl = { .d32 = 0 };
  30         gintsts_t gintsts = { .d32 = 0 };
  31         gahbcfg_t gahbcfg = { .d32 = 0 };
  32         grxfsiz_t grxfsiz = { .d32 = 0 };
  33         ghwcfg3_t hwcfg3 = { .d32 = 0 };
  34         hcintmsk_t hcintmsk = { .d32 = 0 };
  35         gtxfsiz_t gnptxfsiz = { .d32 = 0 };
  36         gtxfsiz_t hptxfsiz = { .d32 = 0 };
  37
  38         const int timeout = 10000;
  39         int i, fifo_blocks, tx_blocks;
  40
  41         /* Wait for AHB idle */
  42         for (i = 0; i < timeout; i++) {
  43                 udelay(1);
  44                 grstctl.d32 = readl(&reg->core.grstctl);
  45                 if (grstctl.ahbidle)
  46                         break;
  47         }
  48         if (i == timeout)
  49                 fatal("DWC2 Init error AHB Idle\n");
  50
  51         /* Restart the Phy Clock */
  52         writel(0x0, &reg->pcgr.pcgcctl);
  53         /* Core soft reset */
  54         grstctl.csftrst = 1;
  55         writel(grstctl.d32, &reg->core.grstctl);
  56         for (i = 0; i < timeout; i++) {
  57                 udelay(1);
  58                 grstctl.d32 = readl(&reg->core.grstctl);
  59                 if (!grstctl.csftrst)
  60                         break;
  61         }
  62         if (i == timeout)
  63                 fatal("DWC2 Init error reset fail\n");
  64
  65         /* Set 16bit PHY if & Force host mode */
  66         gusbcfg.d32 = readl(&reg->core.gusbcfg);
  67         gusbcfg.phyif = 1;
  68         gusbcfg.forcehstmode = 1;
  69         gusbcfg.forcedevmode = 0;
  70         writel(gusbcfg.d32, &reg->core.gusbcfg);
  71         /* Wait for force host mode effect, it may takes 100ms */
  72         for (i = 0; i < timeout; i++) {
  73                 udelay(10);
  74                 gintsts.d32 = readl(&reg->core.gintsts);
  75                 if (gintsts.curmod)
  76                         break;
  77         }
  78         if (i == timeout)
  79                 fatal("DWC2 Init error force host mode fail\n");
  80
  81         /*
  82          * Config FIFO
  83          * The non-periodic tx fifo and rx fifo share one continuous
  84          * piece of IP-internal SRAM.
  85          */
  86
  87         /*
  88          * Read total data FIFO depth from HWCFG3
  89          * this value is in terms of 32-bit words
  90          */
  91         hwcfg3.d32 = readl(&reg->core.ghwcfg3);
  92         /*
  93          * Reserve 2 spaces for the status entries of received packets
  94          * and 2 spaces for bulk and control OUT endpoints. Calculate how
  95          * many blocks can be alloted, assume largest packet size is 512.
  96          * 16 locations reserved for periodic TX .
  97          */
  98         fifo_blocks = (hwcfg3.dfifodepth - 4 - 16) / (512 / 4);
  99         tx_blocks = fifo_blocks / 2;
 100
 101         grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4;
 102         writel(grxfsiz.d32, &reg->core.grxfsiz);
 103         gnptxfsiz.txfstaddr = grxfsiz.rxfdep;
 104         gnptxfsiz.txfdep = tx_blocks * (512 / 4);
 105         writel(gnptxfsiz.d32, &reg->core.gnptxfsiz);
 106         hptxfsiz.txfstaddr = gnptxfsiz.txfstaddr + gnptxfsiz.txfdep;
 107         hptxfsiz.txfdep = 16;
 108         writel(hptxfsiz.d32, &reg->core.hptxfsiz);
 109
 110         /* Init host channels */
 111         hcintmsk.xfercomp = 1;
 112         hcintmsk.xacterr = 1;
 113         hcintmsk.stall = 1;
 114         hcintmsk.chhltd = 1;
 115         hcintmsk.bblerr = 1;
 116         for (i = 0; i < MAX_EPS_CHANNELS; i++)
 117                 writel(hcintmsk.d32, &reg->host.hchn[i].hcintmaskn);
 118
 119         /* Unmask interrupt and configure DMA mode */
 120         gahbcfg.glblintrmsk = 1;
 121         gahbcfg.hbstlen = DMA_BURST_INCR8;
 122         gahbcfg.dmaen = 1;
 123         writel(gahbcfg.d32, &reg->core.gahbcfg);
 124
 125         DWC2_INST(controller)->hprt0 = &reg->host.hprt;
 126
 127         usb_debug("DWC2 init finished!\n");
 128 }
 129
 130 static void dwc2_shutdown(hci_t *controller)
 131 {
 132         detach_controller(controller);
 133         free(DWC2_INST(controller)->dma_buffer);
 134         free(DWC2_INST(controller));
 135         free(controller);
 136 }
 137
 138 /* Test root port device connect status */
 139 static int dwc2_disconnected(hci_t *controller)
 140 {
 141         dwc2_reg_t *reg = DWC2_REG(controller);
 142         hprt_t hprt;
 143
 144         hprt.d32 = readl(&reg->host.hprt);
 145         return !(hprt.prtena && hprt.prtconnsts);
 146 }
 147
 148 #define DWC2_SLEEP_TIME_US      5
 149
 150 /*
 151  * This function returns the actual transfer length when the transfer succeeded
 152  * or an error code if the transfer failed
 153  */
 154 static int
 155 wait_for_complete(endpoint_t *ep, uint32_t ch_num)
 156 {
 157         hcint_t hcint;
 158         hcchar_t hcchar;
 159         hctsiz_t hctsiz;
 160         dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
 161         int timeout = USB_MAX_PROCESSING_TIME_US / DWC2_SLEEP_TIME_US;
 162
 163         /*
 164          * TODO: We should take care of up to three times of transfer error
 165          * retry here, according to the USB 2.0 spec 4.5.2
 166          */
 167         do {
 168                 udelay(DWC2_SLEEP_TIME_US);
 169                 hcint.d32 = readl(&reg->host.hchn[ch_num].hcintn);
 170                 hctsiz.d32 = readl(&reg->host.hchn[ch_num].hctsizn);
 171
 172                 if (hcint.chhltd) {
 173                         writel(hcint.d32, &reg->host.hchn[ch_num].hcintn);
 174                         if (hcint.xfercomp || hcint.ack)
 175                                 return hctsiz.xfersize;
 176                         else if (hcint.nak || hcint.frmovrun)
 177                                 return -HCSTAT_NAK;
 178                         else if (hcint.xacterr)
 179                                 return -HCSTAT_XFERERR;
 180                         else if (hcint.bblerr)
 181                                 return -HCSTAT_BABBLE;
 182                         else if (hcint.stall)
 183                                 return -HCSTAT_STALL;
 184                         else if (hcint.nyet)
 185                                 return -HCSTAT_NYET;
 186                         else
 187                                 return -HCSTAT_UNKNOW;
 188                 }
 189
 190                 if (dwc2_disconnected(ep->dev->controller))
 191                         return -HCSTAT_DISCONNECTED;
 192         } while (timeout--);
 193         /* Release the channel when hit timeout condition */
 194         hcchar.d32 = readl(&reg->host.hchn[ch_num].hccharn);
 195         if (hcchar.chen) {
 196                 /*
 197                  * Programming the HCCHARn register with the chdis and
 198                  * chena bits set to 1 at the same time to disable the
 199                  * channel and the core will generate a channel halted
 200                  * interrupt.
 201                  */
 202                  hcchar.chdis = 1;
 203                  writel(hcchar.d32, &reg->host.hchn[ch_num].hccharn);
 204                  do {
 205                         hcchar.d32 = readl(&reg->host.hchn[ch_num].hccharn);
 206                  } while (hcchar.chen);
 207
 208         }
 209
 210         /* Clear all pending interrupt flags */
 211         hcint.d32 = ~0;
 212         writel(hcint.d32, &reg->host.hchn[ch_num].hcintn);
 213
 214         return -HCSTAT_TIMEOUT;
 215 }
 216
 217 static int
 218 dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 219              uint32_t ch_num, u8 *data_buf, int *short_pkt)
 220 {
 221         uint32_t do_copy;
 222         int ret;
 223         uint32_t packet_cnt;
 224         uint32_t packet_size;
 225         uint32_t transferred = 0;
 226         uint32_t inpkt_length;
 227         hctsiz_t hctsiz = { .d32 = 0 };
 228         hcchar_t hcchar = { .d32 = 0 };
 229         void *aligned_buf;
 230         dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
 231
 232         packet_size = ep->maxpacketsize;
 233         packet_cnt = ALIGN_UP(size, packet_size) / packet_size;
 234         inpkt_length = packet_cnt * packet_size;
 235         /* At least 1 packet should be programmed */
 236         packet_cnt = (packet_cnt == 0) ? 1 : packet_cnt;
 237
 238         /*
 239          * For an IN, this field is the buffer size that the application has
 240          * reserved for the transfer. The application should program this field
 241          * as integer multiple of the maximum packet size for IN transactions.
 242          */
 243         hctsiz.xfersize = (dir == EPDIR_OUT) ? size : inpkt_length;
 244         hctsiz.pktcnt = packet_cnt;
 245         hctsiz.pid = pid;
 246
 247         hcchar.mps = packet_size;
 248         hcchar.epnum = ep->endpoint & 0xf;
 249         hcchar.epdir = dir;
 250         hcchar.eptype = ep->type;
 251         hcchar.multicnt = 1;
 252         hcchar.devaddr = ep->dev->address;
 253         hcchar.chdis = 0;
 254         hcchar.chen = 1;
 255         if (ep->dev->speed == LOW_SPEED)
 256                 hcchar.lspddev = 1;
 257
 258         if (size > DMA_SIZE) {
 259                 usb_debug("Transfer too large: %d\n", size);
 260                 return -1;
 261         }
 262
 263         /*
 264          * Check the buffer address which should be 4-byte aligned and DMA
 265          * coherent
 266          */
 267         do_copy = !dma_coherent(data_buf) || ((uintptr_t)data_buf & 0x3);
 268         aligned_buf = do_copy ? DWC2_INST(ep->dev->controller)->dma_buffer :
 269                       data_buf;
 270
 271         if (do_copy && (dir == EPDIR_OUT))
 272                 memcpy(aligned_buf, data_buf, size);
 273
 274         if (dwc2_disconnected(ep->dev->controller))
 275                 return -HCSTAT_DISCONNECTED;
 276
 277         writel(hctsiz.d32, &reg->host.hchn[ch_num].hctsizn);
 278         writel((uint32_t)virt_to_bus(aligned_buf),
 279                 &reg->host.hchn[ch_num].hcdman);
 280         writel(hcchar.d32, &reg->host.hchn[ch_num].hccharn);
 281
 282         ret = wait_for_complete(ep, ch_num);
 283
 284         if (ret >= 0) {
 285                 /* Calculate actual transferred length */
 286                 transferred = (dir == EPDIR_IN) ? inpkt_length - ret : size;
 287
 288                 if (do_copy && (dir == EPDIR_IN))
 289                         memcpy(data_buf, aligned_buf, transferred);
 290
 291                 if ((short_pkt != NULL) && (dir == EPDIR_IN))
 292                         *short_pkt = (ret > 0) ? 1 : 0;
 293
 294         }
 295
 296         /* Save data toggle */
 297         hctsiz.d32 = readl(&reg->host.hchn[ch_num].hctsizn);
 298         ep->toggle = hctsiz.pid;
 299
 300         if (ret < 0) {
 301                 usb_debug("%s Transfer stop code: %x\n", __func__, ret);
 302                 return ret;
 303         }
 304         return transferred;
 305 }
 306
 307 static int
 308 dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
 309                     uint32_t ch_num, u8 *data_buf, split_info_t *split,
 310                     int *short_pkt)
 311 {
 312         dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
 313         hfnum_t hfnum;
 314         hcsplit_t hcsplit = { .d32 = 0 };
 315         int ret, transferred = 0;
 316
 317         hcsplit.hubaddr = split->hubaddr;
 318         hcsplit.prtaddr = split->hubport;
 319         hcsplit.spltena = 1;
 320         writel(hcsplit.d32, &reg->host.hchn[ch_num].hcspltn);
 321
 322         /* Wait for next frame boundary */
 323         do {
 324                 hfnum.d32 = readl(&reg->host.hfnum);
 325
 326                 if (dwc2_disconnected(ep->dev->controller)) {
 327                         ret = -HCSTAT_DISCONNECTED;
 328                         goto out;
 329                 }
 330         } while (hfnum.frnum % 8 != 0);
 331
 332         /* Handle Start-Split */
 333         ret = dwc2_do_xfer(ep, dir == EPDIR_IN ? 0 : size, pid, dir, ch_num,
 334                            data_buf, NULL);
 335         if (ret < 0)
 336                 goto out;
 337
 338         hcsplit.spltena = 1;
 339         hcsplit.compsplt = 1;
 340         writel(hcsplit.d32, &reg->host.hchn[ch_num].hcspltn);
 341         ep->toggle = pid;
 342
 343         if (dir == EPDIR_OUT)
 344                 transferred += ret;
 345
 346         /* Handle Complete-Split */
 347         do {
 348                 ret = dwc2_do_xfer(ep, dir == EPDIR_OUT ? 0 : size, ep->toggle,
 349                                    dir, ch_num, data_buf, short_pkt);
 350         } while (ret == -HCSTAT_NYET);
 351
 352         if (dir == EPDIR_IN)
 353                 transferred += ret;
 354
 355 out:
 356         /* Clear hcsplit reg */
 357         hcsplit.spltena = 0;
 358         hcsplit.compsplt = 0;
 359         writel(hcsplit.d32, &reg->host.hchn[ch_num].hcspltn);
 360
 361         if (ret < 0)
 362                 return ret;
 363
 364         return transferred;
 365 }
 366
 367 static int dwc2_need_split(usbdev_t *dev, split_info_t *split)
 368 {
 369         if (dev->speed == HIGH_SPEED)
 370                 return 0;
 371
 372         if (closest_usb2_hub(dev, &split->hubaddr, &split->hubport))
 373                 return 0;
 374
 375         return 1;
 376 }
 377
 378 #define USB_FULL_LOW_SPEED_FRAME_US             1000
 379
 380 static int
 381 dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num,
 382               u8 *src, uint8_t skip_nak)
 383 {
 384         split_info_t split;
 385         int ret, short_pkt, transferred = 0;
 386         int timeout = USB_MAX_PROCESSING_TIME_US / USB_FULL_LOW_SPEED_FRAME_US;
 387
 388         ep->toggle = pid;
 389
 390         do {
 391                 short_pkt = 0;
 392                 if (dwc2_need_split(ep->dev, &split)) {
 393 nak_retry:
 394                         ret = dwc2_split_transfer(ep, MIN(ep->maxpacketsize,
 395                               size), ep->toggle, dir, 0, src, &split,
 396                               &short_pkt);
 397
 398                         /*
 399                          * dwc2_split_transfer() waits for the next FullSpeed
 400                          * frame boundary, so we only need to delay 500 us
 401                          * here to have one try per millisecond.
 402                          */
 403                         if (ret == -HCSTAT_NAK && !skip_nak && --timeout) {
 404                                 udelay(USB_FULL_LOW_SPEED_FRAME_US / 2);
 405                                 goto nak_retry;
 406                         }
 407                 } else {
 408                         ret = dwc2_do_xfer(ep, MIN(DMA_SIZE, size), pid, dir, 0,
 409                               src, &short_pkt);
 410                 }
 411
 412                 if (ret < 0)
 413                         return ret;
 414
 415                 size -= ret;
 416                 src += ret;
 417                 transferred += ret;
 418
 419         } while (size > 0 && !short_pkt);
 420
 421         return transferred;
 422 }
 423
 424 static int
 425 dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
 426 {
 427         ep_dir_t data_dir;
 428
 429         if (ep->direction == IN)
 430                 data_dir = EPDIR_IN;
 431         else if (ep->direction == OUT)
 432                 data_dir = EPDIR_OUT;
 433         else
 434                 return -1;
 435
 436         return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 0);
 437 }
 438
 439 static int
 440 dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
 441                    int dalen, u8 *src)
 442 {
 443         int ret = 0;
 444         ep_dir_t data_dir;
 445         endpoint_t *ep = &dev->endpoints[0];
 446
 447         if (dir == IN)
 448                 data_dir = EPDIR_IN;
 449         else if (dir == OUT)
 450                 data_dir = EPDIR_OUT;
 451         else
 452                 return -1;
 453
 454         /* Setup Phase */
 455         if (dwc2_transfer(ep, drlen, PID_SETUP, EPDIR_OUT, 0, setup, 0) < 0)
 456                 return -1;
 457
 458         /* Data Phase */
 459         ep->toggle = PID_DATA1;
 460         if (dalen > 0) {
 461                 ret = dwc2_transfer(ep, dalen, ep->toggle, data_dir, 0, src, 0);
 462                 if (ret < 0)
 463                         return -1;
 464         }
 465
 466         /* Status Phase */
 467         if (dwc2_transfer(ep, 0, PID_DATA1, !data_dir, 0, NULL, 0) < 0)
 468                 return -1;
 469
 470         return ret;
 471 }
 472
 473 static int
 474 dwc2_intr(endpoint_t *ep, int size, u8 *src)
 475 {
 476         ep_dir_t data_dir;
 477
 478         if (ep->direction == IN)
 479                 data_dir = EPDIR_IN;
 480         else if (ep->direction == OUT)
 481                 data_dir = EPDIR_OUT;
 482         else
 483                 return -1;
 484
 485         return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 1);
 486 }
 487
 488 static u32 dwc2_intr_get_timestamp(intr_queue_t *q)
 489 {
 490         hprt_t hprt;
 491         hfnum_t hfnum;
 492         hci_t *controller = q->endp->dev->controller;
 493         dwc_ctrl_t *dwc2 = DWC2_INST(controller);
 494         dwc2_reg_t *reg = DWC2_REG(controller);
 495
 496         hfnum.d32 = readl(&reg->host.hfnum);
 497         hprt.d32 = readl(dwc2->hprt0);
 498
 499         /*
 500          * hfnum.frnum increments when a new SOF is transmitted on
 501          * the USB, and is reset to 0 when it reaches 16'h3FFF
 502          */
 503         switch (hprt.prtspd) {
 504         case PRTSPD_HIGH:
 505                 /* 8 micro-frame per ms for high-speed */
 506                 return hfnum.frnum / 8;
 507         case PRTSPD_FULL:
 508         case PRTSPD_LOW:
 509         default:
 510                 /* 1 micro-frame per ms for high-speed */
 511                 return hfnum.frnum / 1;
 512         }
 513 }
 514
 515 /* create and hook-up an intr queue into device schedule */
 516 static void *
 517 dwc2_create_intr_queue(endpoint_t *ep, const int reqsize,
 518                        const int reqcount, const int reqtiming)
 519 {
 520         intr_queue_t *q = (intr_queue_t *)xzalloc(sizeof(intr_queue_t));
 521
 522         q->data = dma_memalign(4, reqsize);
 523         q->endp = ep;
 524         q->reqsize = reqsize;
 525         q->reqtiming = reqtiming;
 526
 527         return q;
 528 }
 529
 530 static void
 531 dwc2_destroy_intr_queue(endpoint_t *ep, void *_q)
 532 {
 533         intr_queue_t *q = (intr_queue_t *)_q;
 534
 535         free(q->data);
 536         free(q);
 537 }
 538
 539 /*
 540  * read one intr-packet from queue, if available. extend the queue for
 541  * new input. Return NULL if nothing new available.
 542  * Recommended use: while (data=poll_intr_queue(q)) process(data);
 543  */
 544 static u8 *
 545 dwc2_poll_intr_queue(void *_q)
 546 {
 547         intr_queue_t *q = (intr_queue_t *)_q;
 548         int ret = 0;
 549         u32 timestamp = dwc2_intr_get_timestamp(q);
 550
 551         /*
 552          * If hfnum.frnum run overflow it will schedule
 553          * an interrupt transfer immediately
 554          */
 555         if (timestamp - q->timestamp < q->reqtiming)
 556                 return NULL;
 557
 558         q->timestamp = timestamp;
 559
 560         ret = dwc2_intr(q->endp, q->reqsize, q->data);
 561
 562         if (ret > 0)
 563                 return q->data;
 564         else
 565                 return NULL;
 566 }
 567
 568 hci_t *dwc2_init(void *bar)
 569 {
 570         hci_t *controller = new_controller();
 571         controller->instance = xzalloc(sizeof(dwc_ctrl_t));
 572
 573         DWC2_INST(controller)->dma_buffer = dma_malloc(DMA_SIZE);
 574         if (!DWC2_INST(controller)->dma_buffer) {
 575                 usb_debug("Not enough DMA memory for DWC2 bounce buffer\n");
 576                 goto free_dwc2;
 577         }
 578
 579         controller->type = DWC2;
 580         controller->start = dummy;
 581         controller->stop = dummy;
 582         controller->reset = dummy;
 583         controller->init = dwc2_reinit;
 584         controller->shutdown = dwc2_shutdown;
 585         controller->bulk = dwc2_bulk;
 586         controller->control = dwc2_control;
 587         controller->set_address = generic_set_address;
 588         controller->finish_device_config = NULL;
 589         controller->destroy_device = NULL;
 590         controller->create_intr_queue = dwc2_create_intr_queue;
 591         controller->destroy_intr_queue = dwc2_destroy_intr_queue;
 592         controller->poll_intr_queue = dwc2_poll_intr_queue;
 593         controller->reg_base = (uintptr_t)bar;
 594         init_device_entry(controller, 0);
 595
 596         /* Init controller */
 597         controller->init(controller);
 598
 599         /* Setup up root hub */
 600         controller->devices[0]->controller = controller;
 601         controller->devices[0]->init = dwc2_rh_init;
 602         controller->devices[0]->init(controller->devices[0]);
 603         return controller;
 604
 605 free_dwc2:
 606         detach_controller(controller);
 607         free(DWC2_INST(controller));
 608         free(controller);
 609         return NULL;
 610 }