mb/google/brya/var/uldrenite: update gpio settings
[coreboot2.git] / src / drivers / genesyslogic / gl9763e / gl9763e.h
blob647920ca9515dbdd6807c5434842ff4bb26bcf72
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* Definitions for Genesys Logic GL9763E */
5 #include <types.h>
7 #define VHS 0x884
8 #define VHS_REV_MASK (0xF << 16)
9 #define VHS_REV_R (0x0 << 16)
10 #define VHS_REV_M (0x1 << 16)
11 #define VHS_REV_W (0x2 << 16)
12 #define SCR 0x8E0
13 #define SCR_AXI_REQ BIT(9)
15 #define CFG_REG_2 0x8A4
16 #define CFG_REG_2_L0S BIT(11)
17 #define CFG_REG_2_L1DLY_MAX (0x3FF << 19)
19 #define PLL_CTL 0x938
20 #define PLL_CTL_SSC BIT(19)
22 #define EMMC_CTL 0x960
23 #define SLOW_MODE BIT(3)
25 #define PLL_CTL_2 0x93C
26 #define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16)
27 #define MAX_SSC_30000PPM (0xF5C3 << 16)
29 #define HW_VER_2 0x8F8
30 #define HW_VER_MASK 0xFFFF
31 #define REVISION_03 0x0011
33 #define SD_CLKRX_DLY 0x934
34 #define CLK_SRC_MASK (0x3 << 24)
35 #define AFTER_OUTPUT_BUFF (0x0 << 24)
36 #define HS400_RX_DELAY_MASK (0xF << 28)
37 #define HS400_RX_DELAY (0x5 << 28)