mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
[coreboot2.git] / src / drivers / intel / fsp2_0 / fspt_report.c
blob87c08637c112da5e4a81dcab0553b8ce2e9702b4
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/symbols.h>
4 #include <console/console.h>
5 #include <fsp/util.h>
7 /* filled in assembly after FSP-T ran */
8 uintptr_t temp_memory_start;
9 uintptr_t temp_memory_end;
11 void report_fspt_output(void)
13 const struct region fsp_car_region = region_create(
14 temp_memory_start, temp_memory_end - temp_memory_start);
15 const struct region coreboot_car_region = region_create(
16 (uintptr_t)_car_region_start, (uintptr_t)_car_region_size);
18 printk(BIOS_DEBUG, "FSP-T: reported temp_mem region: [0x%08lx,0x%08lx)\n",
19 temp_memory_start, temp_memory_end);
20 if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) {
21 printk(BIOS_ERR, "Wrong CAR region used!\n");
22 printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n");