ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
[coreboot2.git] / src / drivers / spi / amic.c
blobdd16ace700de834e31ec034b92bcc3bea65568b0
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <commonlib/helpers.h>
4 #include <spi_flash.h>
5 #include <spi-generic.h>
7 #include "spi_flash_internal.h"
9 /* A25L-specific commands */
10 #define CMD_A25_WREN 0x06 /* Write Enable */
11 #define CMD_A25_WRDI 0x04 /* Write Disable */
12 #define CMD_A25_RDSR 0x05 /* Read Status Register */
13 #define CMD_A25_WRSR 0x01 /* Write Status Register */
14 #define CMD_A25_READ 0x03 /* Read Data Bytes */
15 #define CMD_A25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
16 #define CMD_A25_PP 0x02 /* Page Program */
17 #define CMD_A25_SE 0x20 /* Sector (4K) Erase */
18 #define CMD_A25_BE 0xd8 /* Block (64K) Erase */
19 #define CMD_A25_CE 0xc7 /* Chip Erase */
20 #define CMD_A25_DP 0xb9 /* Deep Power-down */
21 #define CMD_A25_RES 0xab /* Release from DP, and Read Signature */
23 static const struct spi_flash_part_id flash_table[] = {
25 /* A25L16PU */
26 .id[0] = 0x2015,
27 .nr_sectors_shift = 9,
30 /* A25L16PT */
31 .id[0] = 0x2025,
32 .nr_sectors_shift = 9,
35 /* A25L080 */
36 .id[0] = 0x3014,
37 .nr_sectors_shift = 8,
40 /* A25L016 */
41 .id[0] = 0x3015,
42 .nr_sectors_shift = 9,
45 /* A25L032 */
46 .id[0] = 0x3016,
47 .nr_sectors_shift = 10,
50 /* A25LQ080 */
51 .id[0] = 0x4014,
52 .nr_sectors_shift = 8,
55 /* A25LQ16 */
56 .id[0] = 0x4015,
57 .nr_sectors_shift = 9,
60 /* A25LQ032 */
61 .id[0] = 0x4016,
62 .nr_sectors_shift = 10,
65 /* A25LQ64 */
66 .id[0] = 0x4017,
67 .nr_sectors_shift = 11,
71 const struct spi_flash_vendor_info spi_flash_amic_vi = {
72 .id = VENDOR_ID_AMIC,
73 .page_size_shift = 8,
74 .sector_size_kib_shift = 2,
75 .match_id_mask[0] = 0xffff,
76 .ids = flash_table,
77 .nr_part_ids = ARRAY_SIZE(flash_table),
78 .desc = &spi_flash_pp_0x20_sector_desc,