ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
[coreboot2.git] / src / include / cpu / amd / amd64_save_state.h
blob08b700afaa3d4cf11aa8e5daf2f806d84a99a7f6
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __AMD64_SAVE_STATE_H__
4 #define __AMD64_SAVE_STATE_H__
5 #endif
7 #include <types.h>
8 #include <cpu/x86/smm.h>
10 /* AMD64 x86 SMM State-Save Area
11 * starts @ 0x7e00
13 #define SMM_AMD64_ARCH_OFFSET 0x7e00
14 #define SMM_AMD64_SAVE_STATE_OFFSET \
15 SMM_SAVE_STATE_BEGIN(SMM_AMD64_ARCH_OFFSET)
16 typedef struct {
17 u16 es_selector;
18 u16 es_attributes;
19 u32 es_limit;
20 u64 es_base;
22 u16 cs_selector;
23 u16 cs_attributcs;
24 u32 cs_limit;
25 u64 cs_base;
27 u16 ss_selector;
28 u16 ss_attributss;
29 u32 ss_limit;
30 u64 ss_base;
32 u16 ds_selector;
33 u16 ds_attributds;
34 u32 ds_limit;
35 u64 ds_base;
37 u16 fs_selector;
38 u16 fs_attributfs;
39 u32 fs_limit;
40 u64 fs_base;
42 u16 gs_selector;
43 u16 gs_attributgs;
44 u32 gs_limit;
45 u64 gs_base;
47 u8 reserved0[4];
48 u16 gdtr_limit;
49 u8 reserved1[2];
50 u64 gdtr_base;
52 u16 ldtr_selector;
53 u16 ldtr_attributes;
54 u32 ldtr_limit;
55 u64 ldtr_base;
57 u8 reserved2[4];
58 u16 idtr_limit;
59 u8 reserved3[2];
60 u64 idtr_base;
62 u16 tr_selector;
63 u16 tr_attributes;
64 u32 tr_limit;
65 u64 tr_base;
67 u64 io_restart_rip;
68 u64 io_restart_rcx;
69 u64 io_restart_rsi;
70 u64 io_restart_rdi;
71 u32 smm_io_trap_offset;
72 u32 local_smi_status;
74 u8 io_restart;
75 u8 autohalt_restart;
77 u8 reserved5[6];
79 u64 efer;
81 u8 reserved6[36];
83 u32 smm_revision;
84 u32 smbase;
86 u8 reserved7[68];
88 u64 cr4;
89 u64 cr3;
90 u64 cr0;
91 u64 dr7;
92 u64 dr6;
94 u64 rflags;
95 u64 rip;
96 u64 r15;
97 u64 r14;
98 u64 r13;
99 u64 r12;
100 u64 r11;
101 u64 r10;
102 u64 r9;
103 u64 r8;
105 u64 rdi;
106 u64 rsi;
107 u64 rpb;
108 u64 rsp;
109 u64 rbx;
110 u64 rdx;
111 u64 rcx;
112 u64 rax;
113 } __packed amd64_smm_state_save_area_t;