src/mainboard/amd/mandolin/variants/cereme/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/amd/picasso
   4         # ACP Configuration
   5         register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA"
   6
   7         # Set FADT Configuration
   8         register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
   9         register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
  10
  11         register "has_usb2_phy_tune_params" = "1"
  12
  13         # Controller0 Port0 Default
  14         register "usb_2_port_tune_params[0]" = "{
  15                 .com_pds_tune = 0x03,
  16                 .sq_rx_tune = 0x3,
  17                 .tx_fsls_tune = 0x3,
  18                 .tx_pre_emp_amp_tune = 0x03,
  19                 .tx_pre_emp_pulse_tune = 0x0,
  20                 .tx_rise_tune = 0x1,
  21                 .tx_vref_tune = 0x6,
  22                 .tx_hsxv_tune = 0x3,
  23                 .tx_res_tune = 0x01,
  24         }"
  25
  26         # Controller0 Port1 Default
  27         register "usb_2_port_tune_params[1]" = "{
  28                 .com_pds_tune = 0x03,
  29                 .sq_rx_tune = 0x3,
  30                 .tx_fsls_tune = 0x3,
  31                 .tx_pre_emp_amp_tune = 0x03,
  32                 .tx_pre_emp_pulse_tune = 0x0,
  33                 .tx_rise_tune = 0x1,
  34                 .tx_vref_tune = 0x6,
  35                 .tx_hsxv_tune = 0x3,
  36                 .tx_res_tune = 0x01,
  37         }"
  38
  39         # Controller0 Port2 Default
  40         register "usb_2_port_tune_params[2]" = "{
  41                 .com_pds_tune = 0x03,
  42                 .sq_rx_tune = 0x3,
  43                 .tx_fsls_tune = 0x3,
  44                 .tx_pre_emp_amp_tune = 0x03,
  45                 .tx_pre_emp_pulse_tune = 0x0,
  46                 .tx_rise_tune = 0x1,
  47                 .tx_vref_tune = 0x6,
  48                 .tx_hsxv_tune = 0x3,
  49                 .tx_res_tune = 0x01,
  50         }"
  51
  52         # Controller0 Port3 Default
  53         register "usb_2_port_tune_params[3]" = "{
  54                 .com_pds_tune = 0x03,
  55                 .sq_rx_tune = 0x3,
  56                 .tx_fsls_tune = 0x3,
  57                 .tx_pre_emp_amp_tune = 0x03,
  58                 .tx_pre_emp_pulse_tune = 0x0,
  59                 .tx_rise_tune = 0x1,
  60                 .tx_vref_tune = 0x6,
  61                 .tx_hsxv_tune = 0x3,
  62                 .tx_res_tune = 0x01,
  63         }"
  64
  65         # Controller0 Port4 Default
  66         register "usb_2_port_tune_params[4]" = "{
  67                 .com_pds_tune = 0x03,
  68                 .sq_rx_tune = 0x3,
  69                 .tx_fsls_tune = 0x3,
  70                 .tx_pre_emp_amp_tune = 0x02,
  71                 .tx_pre_emp_pulse_tune = 0x0,
  72                 .tx_rise_tune = 0x1,
  73                 .tx_vref_tune = 0x5,
  74                 .tx_hsxv_tune = 0x3,
  75                 .tx_res_tune = 0x01,
  76         }"
  77
  78         # Controller0 Port5 Default
  79         register "usb_2_port_tune_params[5]" = "{
  80                 .com_pds_tune = 0x03,
  81                 .sq_rx_tune = 0x3,
  82                 .tx_fsls_tune = 0x3,
  83                 .tx_pre_emp_amp_tune = 0x02,
  84                 .tx_pre_emp_pulse_tune = 0x0,
  85                 .tx_rise_tune = 0x1,
  86                 .tx_vref_tune = 0x5,
  87                 .tx_hsxv_tune = 0x3,
  88                 .tx_res_tune = 0x01,
  89         }"
  90
  91         # USB OC pin mapping; all ports share one OC pin
  92         register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"
  93         register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0"
  94         register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0"
  95         register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0"
  96         register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0"
  97         register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0"
  98
  99         # eSPI Configuration
 100         register "common_config.espi_config" = "{
 101                 .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN,
 102                 .generic_io_range[0] = {
 103                         .base = 0x662,
 104                         .size = 8,
 105                 },
 106
 107                 .io_mode = ESPI_IO_MODE_SINGLE,
 108                 .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 109                 .crc_check_enable = 1,
 110                 .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 111                 .periph_ch_en = 0,
 112                 .vw_ch_en = 0,
 113                 .oob_ch_en = 0,
 114                 .flash_ch_en = 0,
 115         }"
 116
 117         # general purpose PCIe clock output configuration
 118         register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 119         register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 120         register "gpp_clk_config[2]" = "GPP_CLK_REQ"
 121         register "gpp_clk_config[3]" = "GPP_CLK_OFF"
 122         register "gpp_clk_config[4]" = "GPP_CLK_REQ"
 123         register "gpp_clk_config[5]" = "GPP_CLK_OFF"
 124         register "gpp_clk_config[6]" = "GPP_CLK_OFF"
 125
 126         register "pspp_policy" = "DXIO_PSPP_BALANCED"
 127
 128         device domain 0 on
 129                 subsystemid 0x1022 0x1510 inherit
 130                 device ref iommu on end
 131                 device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip
 132                 device ref internal_bridge_a on
 133                         device ref gfx on  end # Internal GPU
 134                         device ref gfx_hda on end # Display HDA
 135                         device ref crypto on end # Crypto Coprocessor
 136                         device ref xhci_0 on end # USB 3.1
 137                         device ref xhci_1 off end # USB 3.1
 138                         device ref acp on end # Audio
 139                         device ref hda on end # HDA
 140                         device ref mp2 on  end # non-Sensor Fusion Hub device
 141                 end
 142                 device ref internal_bridge_b on
 143                         device ref sata off end # AHCI
 144                         device ref xgbe_0 off end # integrated Ethernet MAC
 145                         device ref xgbe_1 off end # integrated Ethernet MAC
 146                 end
 147                 device ref lpc_bridge on
 148                         # chip superio/smsc/sio1036 # optional debug card
 149                 end
 150         end # domain
 151
 152         device ref uart_0 on end # console
 153         device ref uart_1 on end
 154
 155 end     # chip soc/amd/picasso