src/mainboard/amd/onyx_poc/devicetree.cb

   1 chip soc/amd/genoa_poc
   2
   3         # USB configuration
   4         register "usb.xhci0_enable" = "1"
   5         register "usb.xhci1_enable" = "1"
   6         # OC pins
   7         register "usb.usb2_oc_pins[0].port0" = "0x0"
   8         register "usb.usb2_oc_pins[0].port1" = "0x1"
   9         register "usb.usb2_oc_pins[0].port2" = "0x0"
  10         register "usb.usb2_oc_pins[0].port3" = "0x1"
  11
  12         register "usb.usb2_oc_pins[1].port0" = "0x0"
  13         register "usb.usb2_oc_pins[1].port1" = "0x1"
  14
  15         register "usb.usb3_oc_pins[0].port0" = "0x0"
  16         register "usb.usb3_oc_pins[0].port1" = "0x1"
  17         register "usb.usb3_oc_pins[0].port2" = "0x0"
  18         register "usb.usb3_oc_pins[0].port3" = "0x1"
  19         register "usb.usb3_oc_pins[1].port0" = "0x0"
  20         register "usb.usb3_oc_pins[1].port1" = "0x1"
  21
  22         register "usb.polarity_cfg_low" = "true"
  23
  24         register "usb.usb3_force_gen1.port0" = "3"
  25         register "usb.usb3_force_gen1.port1" = "3"
  26         register "usb.usb3_force_gen1.port2" = "3"
  27         register "usb.usb3_force_gen1.port3" = "3"
  28
  29         # eSPI configuration
  30         register "common_config.espi_config" = "{
  31                 .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN,
  32                 .io_mode = ESPI_IO_MODE_SINGLE,
  33                 .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
  34                 .crc_check_enable = 1,
  35                 .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
  36                 .periph_ch_en = 0,
  37                 .vw_ch_en = 0,
  38                 .oob_ch_en = 0,
  39                 .flash_ch_en = 0,
  40         }"
  41
  42         # PHY settings
  43         register "usb.usb31_phy_enable" = "1"
  44         register "usb.usb31_phy" = "{
  45                         {0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
  46                         {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
  47                         {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
  48                         {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
  49                         {0x05, 0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
  50                         {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
  51                         {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
  52                         {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
  53                 }"
  54
  55         device domain 0 on
  56                 device ref iommu_0 on end
  57                 device ref rcec_0 on end
  58                 chip vendorcode/amd/opensil/chip/mpio # P2
  59                         register "type" = "IFTYPE_PCIE"
  60                         register "start_lane" = "48"
  61                         register "end_lane" = "63"
  62                         register "gpio_group" = "1"
  63                         register "aspm" = "L1"
  64                         device ref gpp_bridge_0_0_a on end
  65                 end
  66                 chip vendorcode/amd/opensil/chip/mpio # G2
  67                         register "type" = "IFTYPE_PCIE"
  68                         register "start_lane" = "112"
  69                         register "end_lane" = "127"
  70                         register "gpio_group" = "1"
  71                         register "aspm" = "L1"
  72                         register "hotplug" = "ServerExpress"
  73                         device ref gpp_bridge_0_0_b on end
  74                 end
  75                 chip vendorcode/amd/opensil/chip/mpio
  76                         register "type" = "IFTYPE_PCIE"
  77                         register "start_lane" = "128"
  78                         register "end_lane" = "131"
  79                         register "gpio_group" = "1"
  80                         register "aspm" = "L1"
  81                         device ref gpp_bridge_0_0_c on end
  82                 end
  83                 device ref gpp_bridge_0_a on
  84                         device ref xhci_0 on end
  85                         device ref mp0_0 on end
  86                 end
  87                 device ref gpp_bridge_0_b on
  88                         device ref sata_0_0 on end
  89                         device ref sata_0_1 on end
  90                 end
  91         end
  92
  93         device domain 1 on
  94                 device ref iommu_1 on end
  95                 device ref rcec_1 on end
  96                 chip vendorcode/amd/opensil/chip/mpio # P3
  97                         register "type" = "IFTYPE_PCIE"
  98                         register "start_lane" = "16"
  99                         register "end_lane" = "31"
 100                         register "gpio_group" = "1"
 101                         register "aspm" = "L1"
 102                         device ref gpp_bridge_1_0_a on end
 103                 end
 104                 chip vendorcode/amd/opensil/chip/mpio # G3
 105                         register "type" = "IFTYPE_PCIE"
 106                         register "start_lane" = "80"
 107                         register "end_lane" = "95"
 108                         register "gpio_group" = "1"
 109                         register "aspm" = "L1"
 110                         device ref gpp_bridge_1_0_b on end
 111                 end
 112         end
 113
 114         device domain 2 on
 115                 device ref iommu_2 on end
 116                 device ref rcec_2 on end
 117                 chip vendorcode/amd/opensil/chip/mpio # P1
 118                         register "type" = "IFTYPE_PCIE"
 119                         register "start_lane" = "32"
 120                         register "end_lane" = "47"
 121                         register "gpio_group" = "1"
 122                         register "aspm" = "L1"
 123                         register "hotplug" = "ServerExpress"
 124                         device ref gpp_bridge_2_0_a on end
 125                 end
 126                 chip vendorcode/amd/opensil/chip/mpio # G1
 127                         register "type" = "IFTYPE_PCIE"
 128                         register "start_lane" = "64"
 129                         register "end_lane" = "79"
 130                         register "gpio_group" = "1"
 131                         register "aspm" = "L1"
 132                         device ref gpp_bridge_2_0_b on end
 133                 end
 134
 135         end
 136
 137         device domain 3 on
 138                 device ref iommu_3 on end
 139                 device ref rcec_3 on end
 140                 chip vendorcode/amd/opensil/chip/mpio # P0
 141                         register "type" = "IFTYPE_PCIE"
 142                         register "start_lane" = "0"
 143                         register "end_lane" = "15"
 144                         register "gpio_group" = "1"
 145                         register "aspm" = "L1"
 146                         device ref gpp_bridge_3_0_a on end
 147                 end
 148                 chip vendorcode/amd/opensil/chip/mpio # G0
 149                         register "type" = "IFTYPE_PCIE"
 150                         register "start_lane" = "96"
 151                         register "end_lane" = "111"
 152                         register "gpio_group" = "1"
 153                         register "aspm" = "L1"
 154                         device ref gpp_bridge_3_0_b on end
 155                 end
 156                 chip vendorcode/amd/opensil/chip/mpio
 157                         register "type" = "IFTYPE_PCIE"
 158                         register "start_lane" = "132"
 159                         register "end_lane" = "133"
 160                         register "gpio_group" = "1"
 161                         register "aspm" = "L1"
 162                         device ref gpp_bridge_3_0_c on end # WAFL
 163                 end
 164                 chip vendorcode/amd/opensil/chip/mpio
 165                         register "type" = "IFTYPE_PCIE"
 166                         register "start_lane" = "134"
 167                         register "end_lane" = "134"
 168                         register "gpio_group" = "1"
 169                         register "aspm" = "L1"
 170                         register "bmc" = "1"
 171                         device ref gpp_bridge_3_1_c on end # BMC
 172                 end
 173                 chip vendorcode/amd/opensil/chip/mpio
 174                         register "type" = "IFTYPE_PCIE"
 175                         register "start_lane" = "135"
 176                         register "end_lane" = "135"
 177                         register "gpio_group" = "1"
 178                         register "aspm" = "L1"
 179                         device ref gpp_bridge_3_2_c on end # BMC
 180                 end
 181                 device ref gpp_bridge_3_a on
 182                         device ref xhci_3 on end
 183                         device ref mp0_3 on end
 184                 end
 185                 device ref gpp_bridge_3_b on
 186                         device ref sata_3_0 on end
 187                         device ref sata_3_1 on end
 188                 end
 189         end
 190
 191         device ref uart_0 on end
 192         device ref uart_1 on end
 193
 194 end