src/mainboard/amd/pademelon/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/agesawrapper.h>
   4 #include <amdblocks/BiosCallOuts.h>
   5 #include <gpio.h>
   6 #include <soc/southbridge.h>
   7 #include "gpio.h"
   8
   9 /*
  10  * As a rule of thumb, GPIO pins used by coreboot should be initialized at
  11  * bootblock while GPIO pins used only by the OS should be initialized at
  12  * ramstage.
  13  */
  14 static const struct soc_amd_gpio gpio_set_stage_reset[] = {
  15         /* GFX presence detect */
  16         PAD_GPI(GPIO_9, PULL_DOWN),
  17         /* VDDP_VCTRL */
  18         PAD_GPO(GPIO_40, HIGH),
  19         /* PC SPKR */
  20         PAD_NF(GPIO_91, SPKR, PULL_NONE),
  21 };
  22
  23 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
  24 #if CONFIG(HAVE_ACPI_RESUME)
  25         /* PCIE_WAKE - default, do not program */
  26
  27         /* DEVSLP1 */
  28         PAD_NF(GPIO_70, DEVSLP1, PULL_UP),
  29         /* WLAND */
  30         PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3),
  31 #else
  32         /* PCIE_WAKE, SCI */
  33         PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW),
  34         /* DEVSLP1 - default as GPIO, do not program */
  35
  36         /* WLAND - default as GPIO, do not program */
  37
  38 #endif /* HAVE_ACPI_RESUME */
  39         /* BLINK - reselect GPIO OUTPUT HIGH to force BLINK */
  40         PAD_GPO(GPIO_11, HIGH),
  41 };
  42
  43 const struct soc_amd_gpio *early_gpio_table(size_t *size)
  44 {
  45         *size = ARRAY_SIZE(gpio_set_stage_reset);
  46         return gpio_set_stage_reset;
  47 }
  48
  49 const struct soc_amd_gpio *gpio_table(size_t *size)
  50 {
  51         *size = ARRAY_SIZE(gpio_set_stage_ram);
  52         return gpio_set_stage_ram;
  53 }