1 ## SPDX
-License
-Identifier
: GPL
-2.0-only
4 register
"deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN"
6 # Enable Enhanced Intel SpeedStep
7 register
"eist_enable" = "1"
11 register
"PrimaryDisplay" = "Display_iGFX"
14 device ref south_xhci on
15 register
"usb2_ports" = "{
16 [0] = USB2_PORT_MID(OC0), // Front panel (blue)
17 [1] = USB2_PORT_MID(OC0), // Front panel (blue)
18 [2] = USB2_PORT_MID(OC3), // Back panel (black)
19 [3] = USB2_PORT_MID(OC2), // Back panel (blue)
20 [4] = USB2_PORT_MID(OC1), // Back panel (blue)
21 [6] = USB2_PORT_MID(OC1), // Back panel (black)
22 [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot
24 register
"usb3_ports" = "{
25 [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue)
26 [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue)
27 [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue)
28 [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue)
32 #
ME interface is
'off' to avoid HECI reset delay due to HAP
33 device ref heci1 off
end
36 register
"SataSalpSupport" = "1"
37 register
"SataPortsEnable[0]" = "1"
41 device ref pcie_rp21 on
42 register
"PcieRpEnable[20]" = "1"
43 register
"PcieRpClkReqSupport[20]" = "1"
44 register
"PcieRpClkReqNumber[20]" = "3"
45 register
"PcieRpAdvancedErrorReporting[20]" = "1"
46 register
"PcieRpLtrEnable[20]" = "1"
47 register
"PcieRpClkSrcNumber[20]" = "3"
48 register
"PcieRpHotPlug[20]" = "1"
52 device ref pcie_rp5 on
53 register
"PcieRpEnable[4]" = "1"
54 register
"PcieRpClkReqSupport[4]" = "0"
55 register
"PcieRpHotPlug[4]" = "0"
59 device ref pcie_rp8 on
60 register
"PcieRpEnable[7]" = "1"
61 register
"PcieRpClkReqSupport[7]" = "0"
62 register
"PcieRpHotPlug[7]" = "1"
65 # UART0 is exposed on test points on the bottom of the board
67 register
"SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci"
70 device ref lpc_espi on
71 register
"serirq_mode" = "SERIRQ_CONTINUOUS"
73 # I
/O decode
for EMI
/Runtime registers
74 register
"gen1_dec" = "0x007c0a01"
77 chip superio
/smsc
/sch555x
78 device pnp
2e
.0 on # EMI
81 device pnp
2e
.1 off
end #
8042
82 device pnp
2e
.7 on # UART1
87 device pnp
2e
.8 off
end # UART2
88 device pnp
2e.c on # LPC interface
91 device pnp
2e.a on # Runtime registers
94 device pnp
2e.b off
end # Floppy Controller
95 device pnp
2e
.11 off
end # Parallel Port
101 device ref smbus on
end