ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
[coreboot2.git] / src / mainboard / dell / optiplex_3050 / devicetree.cb
blob039709aa4ac450a1b77f8daf5718d6e9a886af86
1 ## SPDX-License-Identifier: GPL-2.0-only
3 chip soc/intel/skylake
4 register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN"
6 # Enable Enhanced Intel SpeedStep
7 register "eist_enable" = "1"
9 device domain 0 on
10 device ref igpu on
11 register "PrimaryDisplay" = "Display_iGFX"
12 end
14 device ref south_xhci on
15 register "usb2_ports" = "{
16 [0] = USB2_PORT_MID(OC0), // Front panel (blue)
17 [1] = USB2_PORT_MID(OC0), // Front panel (blue)
18 [2] = USB2_PORT_MID(OC3), // Back panel (black)
19 [3] = USB2_PORT_MID(OC2), // Back panel (blue)
20 [4] = USB2_PORT_MID(OC1), // Back panel (blue)
21 [6] = USB2_PORT_MID(OC1), // Back panel (black)
22 [8] = USB2_PORT_MID(OC_SKIP), // WiFi slot
24 register "usb3_ports" = "{
25 [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue)
26 [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue)
27 [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue)
28 [3] = USB3_PORT_DEFAULT(OC1), // Back panel (blue)
30 end
32 # ME interface is 'off' to avoid HECI reset delay due to HAP
33 device ref heci1 off end
35 device ref sata on
36 register "SataSalpSupport" = "1"
37 register "SataPortsEnable[0]" = "1"
38 end
40 # M.2 SSD
41 device ref pcie_rp21 on
42 register "PcieRpEnable[20]" = "1"
43 register "PcieRpClkReqSupport[20]" = "1"
44 register "PcieRpClkReqNumber[20]" = "3"
45 register "PcieRpAdvancedErrorReporting[20]" = "1"
46 register "PcieRpLtrEnable[20]" = "1"
47 register "PcieRpClkSrcNumber[20]" = "3"
48 register "PcieRpHotPlug[20]" = "1"
49 end
51 # Realtek LAN
52 device ref pcie_rp5 on
53 register "PcieRpEnable[4]" = "1"
54 register "PcieRpClkReqSupport[4]" = "0"
55 register "PcieRpHotPlug[4]" = "0"
56 end
58 # M.2 WiFi
59 device ref pcie_rp8 on
60 register "PcieRpEnable[7]" = "1"
61 register "PcieRpClkReqSupport[7]" = "0"
62 register "PcieRpHotPlug[7]" = "1"
63 end
65 # UART0 is exposed on test points on the bottom of the board
66 device ref uart0 on
67 register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci"
68 end
70 device ref lpc_espi on
71 register "serirq_mode" = "SERIRQ_CONTINUOUS"
73 # I/O decode for EMI/Runtime registers
74 register "gen1_dec" = "0x007c0a01"
76 # SCH5553
77 chip superio/smsc/sch555x
78 device pnp 2e.0 on # EMI
79 io 0x60 = 0xa00
80 end
81 device pnp 2e.1 off end # 8042
82 device pnp 2e.7 on # UART1
83 io 0x60 = 0x3f8
84 irq 0x0f = 2
85 irq 0x70 = 4
86 end
87 device pnp 2e.8 off end # UART2
88 device pnp 2e.c on # LPC interface
89 io 0x60 = 0x2e
90 end
91 device pnp 2e.a on # Runtime registers
92 io 0x60 = 0xa40
93 end
94 device pnp 2e.b off end # Floppy Controller
95 device pnp 2e.11 off end # Parallel Port
96 end
97 end
99 device ref hda on end
101 device ref smbus on end