mb/google/brya/var/uldrenite: update gpio settings

[coreboot2.git] / src / mainboard / google / brya / variants / gaelin / overridetree.cb

chip soc/intel/alderlake

        register "usb2_ports[2]" = "USB2_PORT_EMPTY"
        register "usb2_ports[3]" = "USB2_PORT_EMPTY"
        register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"     # UFCamera

        register "usb3_ports[2]" = "USB3_PORT_EMPTY"
        register "usb3_ports[3]" = "USB3_PORT_EMPTY"

        register "tcss_ports[2]" = "TCSS_PORT_EMPTY"

        register "serial_io_i2c_mode" = "{
                [PchSerialIoIndexI2C0] = PchSerialIoPci,
                [PchSerialIoIndexI2C1] = PchSerialIoPci,
                [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
                [PchSerialIoIndexI2C3] = PchSerialIoPci,
                [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
                [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
        }"

        register "serial_io_gspi_mode" = "{
                [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
                [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
        }"

        # Enable eDP in Port A
        register "ddi_portA_config" = "1"

        register "ddi_ports_config" = "{
                [DDI_PORT_A] = DDI_ENABLE_HPD,
                [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
        }"

        register "sagv" = "SaGv_Enabled"

        # Intel Common SoC Config
        #+-------------------+---------------------------+
        #| Field             |  Value                    |
        #+-------------------+---------------------------+
        #| I2C0              | Audio                     |
        #| I2C1              | cr50 TPM. Early init is   |
        #|                   | required to set up a BAR  |
        #|                   | for TPM communication     |
        #| I2C3              | TouchScreen               |
        #+-------------------+---------------------------+
        register "common_soc_config" = "{
                .i2c[0] = {
                        .speed = I2C_SPEED_FAST,
                },
                .i2c[1] = {
                        .early_init = 1,
                        .speed = I2C_SPEED_FAST,
                        .rise_time_ns = 600,
                        .fall_time_ns = 400,
                        .data_hold_time_ns = 50,
                },
                .i2c[3] = {
                        .speed = I2C_SPEED_FAST,
                        .rise_time_ns = 600,
                        .fall_time_ns = 400,
                        .data_hold_time_ns = 50,
                },
        }"

        device domain 0 on
                device ref pcie4_0 on
                        # Enable CPU PCIE RP 1 using CLK 0
                        register "cpu_pcie_rp[CPU_RP(1)]" = "{
                                .clk_req = 0,
                                .clk_src = 0,
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                        }"
                end
                device ref tcss_xhci on
                        chip drivers/usb/acpi
                                device ref tcss_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))"
                                                register "usb_lpm_incapable" = "true"
                                                device ref tcss_usb3_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-C Port C1 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
                                                register "usb_lpm_incapable" = "true"
                                                device ref tcss_usb3_port2 on end
                                        end
                                end
                        end
                end
                device ref xhci on
                        chip drivers/usb/acpi
                                device ref xhci_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))"
                                                device ref usb2_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-C Port C1 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
                                                device ref usb2_port2 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""UFCamera""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                register "has_power_resource" = "1"
                                                register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A17)"
                                                register "enable_delay_ms" = "20"
                                                device ref usb2_port5 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A3 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
                                                device ref usb2_port6 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A2 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))"
                                                device ref usb2_port7 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A1 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))"
                                                device ref usb2_port8 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A0 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
                                                device ref usb2_port9 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Bluetooth""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
                                                device ref usb2_port10 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A0 (MLB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
                                                device ref usb3_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A1 (MLB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))"
                                                device ref usb3_port2 on end
                                        end
                                end
                        end
                end
                device ref i2c0 on
                        chip drivers/i2c/nau8825
                                register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
                                register "jkdet_enable" = "1"
                                register "jkdet_pull_enable" = "0"
                                register "jkdet_pull_up" = "0"
                                register "jkdet_polarity" = "1"      # ActiveLow
                                register "vref_impedance" = "2"      # 125kOhm
                                register "micbias_voltage" = "6"     # 2.754
                                register "sar_threshold_num" = "4"
                                register "sar_threshold[0]" = "0x0C"
                                register "sar_threshold[1]" = "0x1C"
                                register "sar_threshold[2]" = "0x38"
                                register "sar_threshold[3]" = "0x60"
                                register "sar_hysteresis" = "1"
                                register "sar_voltage" = "0"          # VDDA
                                register "sar_compare_time" = "0"     # 500ns
                                register "sar_sampling_time" = "0"    # 2us
                                register "short_key_debounce" = "2"   # 100ms
                                register "jack_insert_debounce" = "7" # 512ms
                                register "jack_eject_debounce" = "7"  # 512ms
                                device i2c 1a on end
                        end # Audio Nau8825
                end # I2C0
                device ref i2c3 on
                        chip drivers/i2c/hid
                                register "generic.hid" = ""LM230001""
                                register "generic.desc" = ""LM238 Touchscreen""
                                register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
                                register "generic.detect" = "1"
                                register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
                                register "generic.enable_delay_ms" = "6"
                                register "generic.has_power_resource" = "1"
                                device i2c 34 on end
                        end
                end # I2C3
                device ref pcie_rp5 on
                        # Enable PCIE 5 using clk 2
                        register "pch_pcie_rp[PCH_RP(5)]" = "{
                                .clk_src = 2,
                                .clk_req = 2,
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                        }"
                        chip soc/intel/common/block/pcie/rtd3
                                register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
                                register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
                                register "srcclk_pin" = "2"
                                device generic 0 on end
                        end
                end #PCIE5 WLAN
                device ref pcie_rp7 on
                        # Enable PCIE 7 using clk 6
                        register "pch_pcie_rp[PCH_RP(7)]" = "{
                                .clk_src = 6,
                                .clk_req = 6,
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                        }"
                        chip drivers/net
                                register "customized_leds" = "0x0843"
                                register "wake" = "GPE0_DW0_07" #GPP_A7
                                register "device_index" = "0"
                                device pci 00.0 on end
                        end
                end #PCIE7 RTL8111K Ethernet NIC
                device ref pcie_rp8 off end
                device ref pch_espi on
                        chip ec/google/chromeec
                                use conn0 as mux_conn[0]
                                use conn1 as mux_conn[1]
                                device pnp 0c09.0 on end
                        end
                end
                device ref pmc hidden
                        chip drivers/intel/pmc_mux
                                device generic 0 on
                                        chip drivers/intel/pmc_mux/conn
                                                use usb2_port1 as usb2_port
                                                use tcss_usb3_port1 as usb3_port
                                                device generic 0 alias conn0 on end
                                        end
                                        chip drivers/intel/pmc_mux/conn
                                                use usb2_port2 as usb2_port
                                                use tcss_usb3_port2 as usb3_port
                                                device generic 1 alias conn1 on end
                                        end
                                end
                        end
                end
                device ref hda on
                        chip drivers/generic/alc1015
                                register "hid" = ""RTL1015""
                                device generic 0 on end
                        end # RT1015 Amplifier
                end # Intel HDA
        end
end