1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <commonlib/helpers.h>
8 /* Pad configuration in ramstage */
9 static const struct pad_config override_gpio_table
[] = {
10 /* A6 : ESPI_ALERT1# ==> NC */
12 /* A7 : SRCCLK_OE7# ==> NC */
14 /* A8 : SRCCLKREQ7# ==> NC */
16 /* A12 : SATAXPCIE1 ==> NC */
17 PAD_NC(GPP_A12
, NONE
),
18 /* A14 : USB_OC1# ==> NC */
19 PAD_NC(GPP_A14
, NONE
),
20 /* A15 : USB_OC2# ==> NC */
21 PAD_NC(GPP_A15
, NONE
),
22 /* A18 : DDSP_HPDB ==> NC */
23 PAD_NC(GPP_A18
, NONE
),
24 /* A21 : DDPC_CTRCLK ==> NC */
25 PAD_NC(GPP_A21
, NONE
),
26 /* A22 : DDPC_CTRLDATA ==> NC */
27 PAD_NC(GPP_A22
, NONE
),
29 /* B3 : PROC_GP2 ==> NC */
30 PAD_NC_LOCK(GPP_B3
, NONE
, LOCK_CONFIG
),
31 /* B5 : ISH_I2C0_SDA ==> NC */
32 PAD_NC_LOCK(GPP_B5
, NONE
, LOCK_CONFIG
),
33 /* B6 : ISH_I2C0_SCL ==> NC */
34 PAD_NC_LOCK(GPP_B6
, NONE
, LOCK_CONFIG
),
36 /* C3 : SML0CLK ==> NC */
38 /* C4 : SML0DATA ==> NC */
41 /* D3 : ISH_GP3 ==> NC */
42 PAD_NC_LOCK(GPP_D3
, NONE
, LOCK_CONFIG
),
43 /* D5 : SRCCLKREQ0# ==> NC */
45 /* D9 : ISH_SPI_CS# ==> NC */
46 PAD_NC_LOCK(GPP_D9
, NONE
, LOCK_CONFIG
),
47 /* D15 : ISH_UART0_RTS# ==> NC */
48 PAD_NC_LOCK(GPP_D15
, NONE
, LOCK_CONFIG
),
49 /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
50 PAD_CFG_GPO_LOCK(GPP_D16
, 1, LOCK_CONFIG
),
51 /* D17 : UART1_RXD ==> NC */
52 PAD_NC_LOCK(GPP_D17
, NONE
, LOCK_CONFIG
),
54 /* E0 : SATAXPCIE0 ==> NC */
56 /* E3 : PROC_GP0 ==> NC */
58 /* E4 : SATA_DEVSLP0 ==> NC */
60 /* E7 : PROC_GP1 ==> NC */
62 /* E10 : THC0_SPI1_CS# ==> NC */
63 PAD_NC_LOCK(GPP_E10
, NONE
, LOCK_CONFIG
),
64 /* E16 : RSVD_TP ==> NC */
65 PAD_NC(GPP_E16
, NONE
),
66 /* E17 : THC0_SPI1_INT# ==> NC */
67 PAD_NC_LOCK(GPP_E17
, NONE
, LOCK_CONFIG
),
68 /* E18 : DDP1_CTRLCLK ==> NC */
69 PAD_NC(GPP_E18
, NONE
),
70 /* E20 : DDP2_CTRLCLK ==> NC */
71 PAD_NC(GPP_E20
, NONE
),
73 /* F6 : CNV_PA_BLANKING ==> NC */
75 /* F19 : SRCCLKREQ6# ==> NC */
76 PAD_NC(GPP_F19
, NONE
),
77 /* F20 : EXT_PWR_GATE# ==> NC */
78 PAD_NC(GPP_F20
, NONE
),
79 /* F21 : EXT_PWR_GATE2# ==> NC */
80 PAD_NC(GPP_F21
, NONE
),
82 /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA_P2 */
83 PAD_CFG_NF_LOCK(GPP_H6
, NONE
, NF1
, LOCK_CONFIG
),
84 /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL_P2 */
85 PAD_CFG_NF_LOCK(GPP_H7
, NONE
, NF1
, LOCK_CONFIG
),
86 /* H8 : I2C4_SDA ==> NC */
88 /* H9 : I2C4_SCL ==> NC */
90 /* H13 : I2C7_SCL ==> EN_PP3300_SD */
91 PAD_CFG_GPO_LOCK(GPP_H13
, 1, LOCK_CONFIG
),
92 /* H15 : DDPB_CTRLCLK ==> NC */
93 PAD_NC(GPP_H15
, NONE
),
94 /* H17 : DDPB_CTRLDATA ==> NC*/
95 PAD_NC(GPP_H17
, NONE
),
96 /* H19 : SRCCLKREQ4# ==> NC */
97 PAD_NC(GPP_H19
, NONE
),
98 /* H21 : IMGCLKOUT2 ==> NC */
99 PAD_NC(GPP_H21
, NONE
),
100 /* H22 : IMGCLKOUT3 ==> NC */
101 PAD_NC(GPP_H22
, NONE
),
102 /* H23 : SRCCLKREQ5# ==> NC */
103 PAD_NC(GPP_H23
, NONE
),
105 /* S4 : SNDW2_CLK ==> NC */
106 PAD_NC(GPP_S4
, NONE
),
107 /* S5 : SNDW2_DATA ==> NC */
108 PAD_NC(GPP_S5
, NONE
),
109 /* S6 : SNDW3_CLK ==> NC */
110 PAD_NC(GPP_S6
, NONE
),
111 /* S7 : SNDW3_DATA ==> NC */
112 PAD_NC(GPP_S7
, NONE
),
114 /* GPD11: LANPHYC ==> NC */
118 /* Early pad configuration in bootblock */
119 static const struct pad_config early_gpio_table
[] = {
120 /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
121 PAD_CFG_GPI_APIC(GPP_A13
, NONE
, PLTRST
, LEVEL
, INVERT
),
123 /* B4 : PROC_GP3 ==> SSD_PERST_L */
124 PAD_CFG_GPO(GPP_B4
, 0, DEEP
),
125 /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA_P2 */
126 PAD_CFG_NF(GPP_H6
, NONE
, DEEP
, NF1
),
127 /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL_P2 */
128 PAD_CFG_NF(GPP_H7
, NONE
, DEEP
, NF1
),
130 * D1 : ISH_GP1 ==> FP_RST_ODL
131 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
132 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
133 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
134 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
135 * FPMCU not working after a S3 resume. This is a known issue.
137 PAD_CFG_GPO(GPP_D1
, 0, DEEP
),
138 /* D2 : ISH_GP2 ==> EN_FP_PWR */
139 PAD_CFG_GPO(GPP_D2
, 1, DEEP
),
140 /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
141 PAD_CFG_GPO(GPP_D11
, 1, DEEP
),
143 /* E0 : SATAXPCIE0 ==> NC */
144 PAD_NC(GPP_E0
, NONE
),
145 /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
146 PAD_CFG_GPI(GPP_E13
, NONE
, DEEP
),
147 /* E15 : RSVD_TP ==> PCH_WP_OD */
148 PAD_CFG_GPI_GPIO_DRIVER(GPP_E15
, NONE
, DEEP
),
149 /* E16 : RSVD_TP ==> NC */
150 PAD_NC(GPP_E16
, NONE
),
151 /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
152 PAD_CFG_GPI(GPP_F18
, NONE
, DEEP
),
153 /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
154 PAD_CFG_NF(GPP_H10
, NONE
, DEEP
, NF2
),
155 /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
156 PAD_CFG_NF(GPP_H11
, NONE
, DEEP
, NF2
),
157 /* H13 : I2C7_SCL ==> EN_PP3300_SD */
158 PAD_CFG_GPO(GPP_H13
, 1, DEEP
),
161 static const struct pad_config romstage_gpio_table
[] = {
162 /* B4 : PROC_GP3 ==> SSD_PERST_L */
163 PAD_CFG_GPO(GPP_B4
, 1, DEEP
),
165 /* Enable touchscreen, hold in reset */
166 /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
167 PAD_CFG_GPO(GPP_C0
, 1, DEEP
),
168 /* C1 : SMBDATA ==> USI_RST_L */
169 PAD_CFG_GPO(GPP_C1
, 0, DEEP
),
171 /* D1 : ISH_GP1 ==> FP_RST_ODL */
172 PAD_CFG_GPO(GPP_D1
, 0, DEEP
),
173 /* D2 : ISH_GP2 ==> EN_FP_PWR */
174 PAD_CFG_GPO(GPP_D2
, 0, DEEP
),
175 /* D18 : UART1_TXD ==> SD_PE_RST_L */
176 PAD_CFG_GPO(GPP_D18
, 1, DEEP
),
179 const struct pad_config
*variant_gpio_override_table(size_t *num
)
181 *num
= ARRAY_SIZE(override_gpio_table
);
182 return override_gpio_table
;
185 const struct pad_config
*variant_early_gpio_table(size_t *num
)
187 *num
= ARRAY_SIZE(early_gpio_table
);
188 return early_gpio_table
;
191 const struct pad_config
*variant_romstage_gpio_table(size_t *num
)
193 *num
= ARRAY_SIZE(romstage_gpio_table
);
194 return romstage_gpio_table
;