src/mainboard/google/cyan/variants/banon/overridetree.cb

   1 chip soc/intel/braswell
   2
   3         register "Usb2Port0PerPortPeTxiSet" = "7"
   4         register "Usb2Port0PerPortTxiSet" = "6"
   5         register "Usb2Port0IUsbTxEmphasisEn" = "3"
   6         register "Usb2Port0PerPortTxPeHalf" = "1"
   7         register "Usb2Port1PerPortPeTxiSet" = "7"
   8         register "Usb2Port1PerPortTxiSet" = "6"
   9         register "Usb2Port1IUsbTxEmphasisEn" = "3"
  10         register "Usb2Port1PerPortTxPeHalf" = "1"
  11         register "Usb2Port2PerPortPeTxiSet" = "7"
  12         register "Usb2Port2PerPortTxiSet" = "6"
  13         register "Usb2Port2IUsbTxEmphasisEn" = "3"
  14         register "Usb2Port2PerPortTxPeHalf" = "1"
  15         register "Usb2Port3PerPortPeTxiSet" = "7"
  16         register "Usb2Port3PerPortTxiSet" = "6"
  17         register "Usb2Port3IUsbTxEmphasisEn" = "3"
  18         register "Usb2Port3PerPortTxPeHalf" = "1"
  19         register "Usb2Port4PerPortPeTxiSet" = "7"
  20         register "Usb2Port4PerPortTxiSet" = "6"
  21         register "Usb2Port4IUsbTxEmphasisEn" = "3"
  22         register "Usb2Port4PerPortTxPeHalf" = "1"
  23
  24         device domain 0 on end
  25
  26 end