src/mainboard/google/fatcat/variants/felino/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <boardid.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage*/
   9 static const struct pad_config gpio_table[] = {
  10         /* GPP_A00:     ESPI_IO0_EC_R */
  11         /*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
  12
  13         /* GPP_A01:     ESPI_IO1_EC_R */
  14         /*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
  15
  16         /* GPP_A02:     ESPI_IO2_EC_R */
  17         /*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
  18
  19         /* GPP_A03:     ESPI_IO3_EC_R */
  20         /*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
  21
  22         /* GPP_A04:     ESPI_CS0_EC_R_N */
  23         /*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
  24
  25         /* GPP_A05:     ESPI_CLK_EC_R */
  26         /*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
  27
  28         /* GPP_A06:     ESPI_RST_EC_R_N */
  29         /*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
  30
  31         /* GPP_A08:     MIPI_RGB_XSHUTDN */
  32         PAD_CFG_GPO(GPP_A08, 1, PLTRST),
  33         /* GPP_A09:     MIPI_RGB_OSC_EN */
  34         PAD_CFG_GPO(GPP_A09, 1, PLTRST),
  35         /* GPP_A10:     WWAN_RF_DISABLE_ODL */
  36         PAD_CFG_GPO(GPP_A10, 1, PLTRST),
  37         /* GPP_A11:     WLAN_SOC_RST_N */
  38         PAD_CFG_GPO(GPP_A11, 1, PLTRST),
  39         /* GPP_A12:     WAKE_PCIE_N_SOC */
  40         PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
  41         /* GPP_A13:     Not used */
  42         PAD_NC(GPP_A13, NONE),
  43         /* GPP_A15:     HW_ID1 */
  44         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  45         /* GPP_A16:     BT_RF_KILL_N */
  46         PAD_CFG_GPO(GPP_A16, 1, DEEP),
  47         /* GPP_A17:     PCH_WLAN_OFF_N */
  48         PAD_CFG_GPO(GPP_A17, 1, DEEP),
  49
  50         /* GPP_B00:     TYPEC_PD_SOC_CLK */
  51         PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
  52         /* GPP_B01:     TYPEC_PD_SOC_DAT */
  53         PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
  54         /* GPP_B02:     I2C_SDA_E3_SOC */
  55         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
  56         /* GPP_B03:     I2C_SCL_E3_SOC */
  57         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
  58         /* GPP_B04:     NC */
  59         PAD_NC(GPP_B04, NONE),
  60         /* GPP_B05:     MIPI_IR_LED_PWM */
  61         PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
  62         /* GPP_B06:     NC */
  63         PAD_NC(GPP_B06, NONE),
  64         /* GPP_B07:     NC */
  65         PAD_NC(GPP_B07, NONE),
  66         /* GPP_B08:     NC */
  67         PAD_NC(GPP_B08, NONE),
  68         /* GPP_B09:     NC */
  69         PAD_NC(GPP_B09, NONE),
  70         /* GPP_B10:     SOC_DP1_HDMI_HPD */
  71         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
  72         /* GPP_B11:     PD1_OC_P0_P1_N */
  73         PAD_NC(GPP_B11, NONE),
  74         /* GPP_B12:     SLP_S0_SOC_N */
  75         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  76         /* GPP_B13:     PLT_RST_N */
  77         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  78         /* GPP_B14:     NC */
  79         PAD_NC(GPP_B14, NONE),
  80         /* GPP_B15:     USB_A_OC3_L */
  81         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
  82         /* GPP_B16:     NC */
  83         PAD_NC(GPP_B16, NONE),
  84         /* GPP_B17:     NC */
  85         PAD_NC(GPP_B17, NONE),
  86         /* GPP_B18:     ISH_I2C_EC_SDA */
  87         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
  88         /* GPP_B19:     ISH_I2C_EC_SCL */
  89         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
  90         /* GPP_B20:     I2C2_SOC_SDA */
  91         PAD_CFG_GPO(GPP_B20, 1, PLTRST),
  92         /* GPP_B21:     I2C2_SOC_SCL */
  93         PAD_CFG_GPO(GPP_B21, 0, DEEP),
  94         /* GPP_B22:     Cable_INT_N */
  95         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
  96         /* GPP_B23:     HW_ID0 */
  97         PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
  98         /* GPP_B24:     ESPI_ALERT0_N */
  99         PAD_NC(GPP_B24, NONE),
 100         /* GPP_B25:     MIPI_RGB_LDO_EN */
 101         PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
 102
 103         /* GPP_C00:     NC */
 104         PAD_NC(GPP_C00, NONE),
 105         /* GPP_C01:     NC */
 106         PAD_NC(GPP_C01, NONE),
 107         /* GPP_C02:     GPPC_C2_SMB_ALERT_N */
 108         PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1),
 109         /* GPP_C03:     SMBUS_CLK0 */
 110         PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
 111         /* GPP_C04:     SMBUS_DAT0 */
 112         PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
 113         /* GPP_C05:     GPPC_C5 */
 114         PAD_NC(GPP_C05, NONE),
 115         /* GPP_C06:     NC */
 116         PAD_NC(GPP_C06, NONE),
 117         /* GPP_C07:     NC */
 118         PAD_NC(GPP_C07, NONE),
 119         /* GPP_C08:     PCH_WP_OD */
 120         PAD_CFG_GPO(GPP_C08, 1, PLTRST),
 121         /* GPP_C09:     PCIE_CLKREQ_SSD1_N */
 122         PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
 123         /* GPP_C10:     NC */
 124         PAD_NC(GPP_C10, NONE),
 125         /* GPP_C11:     NC */
 126         PAD_NC(GPP_C11, NONE),
 127         /* GPP_C12:     NC */
 128         PAD_NC(GPP_C12, NONE),
 129         /* GPP_C13:     PCIE_CLKREQ_WLAN_N */
 130         PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 131         /* GPP_C14:     NC */
 132         PAD_NC(GPP_C14, NONE),
 133         /* GPP_C15:     GPP_C15 */
 134         PAD_CFG_GPO(GPP_C15, 1, PLTRST),
 135         /* GPP_C16:     NC  */
 136         PAD_NC(GPP_C16, NONE),
 137         /* GPP_C17:     NC  */
 138         PAD_NC(GPP_C17, NONE),
 139         /* GPP_C18:     TCP3_DDC_SCL  */
 140         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 141         /* GPP_C19:     TCP3_DDC_SDA */
 142         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 143         /* GPP_C20:     TBT_LSX1_TXD */
 144         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 145         /* GPP_C21:     TBT_LSX1_RXD */
 146         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 147         /* GPP_C22:     TBT_LSX0_TXD */
 148         PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
 149         /* GPP_C23:     TBT_LSX0_RXD */
 150         PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 151
 152         /* GPP_D00:     MIPI_RGB_IR_MCLK */
 153         PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
 154         /* GPP_D01:     ALS_I2C_SDA */
 155         PAD_CFG_NF(GPP_D01, NONE, DEEP, NF3),
 156         /* GPP_D02:     ALS_I2C_SCL */
 157         PAD_CFG_NF(GPP_D02, NONE, DEEP, NF3),
 158         /* GPP_D03:     SLP_S0_GATE_R */
 159         PAD_CFG_GPO(GPP_D03, 1, PLTRST),
 160         /* GPP_D04:     MIPI_RGB_MCLK */
 161         PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
 162         /* GPP_D05:     UART0_ISH_RX_DBG_TX_U */
 163         PAD_CFG_NF(GPP_D05, NONE, DEEP, NF1),
 164         /* GPP_D06:     UART0_ISH_TX_DBG_RX_U */
 165         PAD_CFG_NF(GPP_D06, NONE, DEEP, NF1),
 166         /* GPP_D07:     CAM_VDD_EN_SOC */
 167         PAD_CFG_GPO(GPP_D07, 1, PLTRST),
 168         /* GPP_D08:     NC */
 169         PAD_NC(GPP_D08, NONE),
 170         /* GPP_D09:     USB_MUX_SEL */
 171         PAD_CFG_GPO(GPP_D09, 1, PLTRST),
 172         /* GPP_D10:     PMC_WLAN_CLK */
 173         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
 174         /* GPP_D11:     CNV_PCM_SYNC */
 175         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
 176         /* GPP_D12:     PMC_SOC_OUT */
 177         PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
 178         /* GPP_D13:     PMC_SOC_IN */
 179         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
 180         /* GPP_D14:     NC */
 181         PAD_NC(GPP_D14, NONE),
 182         /* GPP_D15:     NC */
 183         PAD_NC(GPP_D15, NONE),
 184         /* GPP_D16:     PCH_DMIC_CLK1 */
 185         PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
 186         /* GPP_D17:     PCH_DMIC_DATA1 */
 187         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
 188         /* GPP_D18:     PCIE_CLKREQ_SD_N */
 189         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 190         /* GPP_D19:     NC */
 191         PAD_NC(GPP_D19, NONE),
 192         /* GPP_D20:     NC */
 193         PAD_NC(GPP_D20, NONE),
 194         /* GPP_D21:     NC */
 195         PAD_NC(GPP_D21, NONE),
 196         /* GPP_D22:     DG_I3C_SDA */
 197         PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 198         /* GPP_D23:     DG_I3C_SCL */
 199         PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 200         /* GPP_D24:     MIPI_IR_LDO_EN */
 201         PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
 202         /* GPP_D25:     MIPI_IR_OSC_EN */
 203         PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
 204
 205         /* GPP_E01:     SLOW_R */
 206         PAD_CFG_GPI(GPP_E01, NONE, PLTRST),
 207         /* GPP_E02:     NC  */
 208         PAD_NC(GPP_E02, NONE),
 209         /* GPP_E03:     NC */
 210         PAD_NC(GPP_E03, NONE),
 211         /* GPP_E05:     NC */
 212         PAD_NC(GPP_E05, NONE),
 213         /* GPP_E06:     GPP_E06 */
 214         PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
 215         /* GPP_E07:     NC */
 216         PAD_NC(GPP_E07, NONE),
 217         /* GPP_E08:     NC */
 218         PAD_NC(GPP_E08, NONE),
 219         /* GPP_E09:     NC */
 220         PAD_NC(GPP_E09, NONE),
 221         /* GPP_E10:     NC */
 222         PAD_NC(GPP_E10, NONE),
 223         /* GPP_E11:     NC */
 224         PAD_NC(GPP_E11, NONE),
 225         /* GPP_E12:     I2C0_SOC_SCL */
 226         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 227         /* GPP_E13:     I2C0_SOC_SDA */
 228         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 229         /* GPP_E14:     NC */
 230         PAD_NC(GPP_E14, NONE),
 231         /* GPP_E15:     NC */
 232         PAD_NC(GPP_E15, NONE),
 233         /* GPP_E16:     NC */
 234         PAD_NC(GPP_E16, NONE),
 235         /* GPP_E17:     NC */
 236         PAD_NC(GPP_E17, NONE),
 237         /* GPP_E18:     TOUCHPAD_INT_N */
 238         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
 239         /* GPP_E19:     HW_ID5 */
 240         PAD_CFG_GPO(GPP_E19, 1, PLTRST),
 241         /* GPP_E20:     HW_ID4 */
 242         PAD_CFG_GPO(GPP_E20, 1, PLTRST),
 243         /* GPP_E21:     TYPEC_PD_SOC_INT */
 244         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 245         /* GPP_E22:     MIPI_IR_XSHUTDN */
 246         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
 247
 248         /* GPP_F00:     CNV_BRI_DT */
 249         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
 250         /* GPP_F01:     CNV_BRI_RSP_SOC */
 251         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
 252         /* GPP_F02:     CNV_RGI_DT */
 253         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
 254         /* GPP_F03:     CNV_RGI_RSP_SOC */
 255         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
 256         /* GPP_F04:     CNV_RF_RESET_R_N */
 257         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 258         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
 259         /* GPP_F05:     CRF_CLKREQ_R */
 260         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 261         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
 262         /* GPP_F06:     NC */
 263         PAD_NC(GPP_F06, NONE),
 264         /* GPP_F07:     NC */
 265         PAD_NC(GPP_F07, NONE),
 266         /* GPP_F08:     NC */
 267         PAD_NC(GPP_F08, NONE),
 268         /* GPP_F09:     NC */
 269         PAD_NC(GPP_F09, NONE),
 270         /* GPP_F10:     HW_ID7 */
 271         PAD_CFG_GPO(GPP_F10, 0, PLTRST),
 272         /* GPP_F11:     TC_RETIMER_FORCE_PWR */
 273         PAD_CFG_GPO(GPP_F11, 1, DEEP),
 274         /* GPP_F12:     NC */
 275         PAD_NC(GPP_F12, NONE),
 276         /* GPP_F13:     NC */
 277         PAD_NC(GPP_F13, NONE),
 278         /* GPP_F14:     NC */
 279         PAD_NC(GPP_F14, NONE),
 280         /* GPP_F15:     GSC_PCH_INT_ODL */
 281         PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 282         /* GPP_F16:     NC */
 283         PAD_NC(GPP_F16, NONE),
 284         /* GPP_F17:     NC */
 285         PAD_NC(GPP_F17, NONE),
 286         /* GPP_F18:     NC */
 287         PAD_NC(GPP_F18, NONE),
 288         /* GPP_F19:     GPP_F19 */
 289         PAD_CFG_GPO(GPP_F19, 0, PLTRST),
 290         /* GPP_F20:     NC */
 291         PAD_NC(GPP_F20, NONE),
 292         /* GPP_F22:     NC */
 293         PAD_NC(GPP_F22, NONE),
 294         /* GPP_F23:     NC */
 295         PAD_NC(GPP_F23, NONE),
 296
 297         /* GPP_H00:     GPP_H00 */
 298         PAD_NC(GPP_H00, NONE),
 299         /* GPP_H01:     GPP_H01 */
 300         PAD_NC(GPP_H01, NONE),
 301         /* GPP_H02:     GPP_H02 */
 302         PAD_NC(GPP_H02, NONE),
 303         /* GPP_H03:     NC */
 304         PAD_NC(GPP_H03, NONE),
 305         /* GPP_H04:     MIPI_IR_SDA */
 306         PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
 307         /* GPP_H05:     MIPI_IR_SCL */
 308         PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
 309         /* GPP_H06:     CAM_I2C_DAT_CONN */
 310         PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 311         /* GPP_H07:     CAM_I2C_CLK_CONN */
 312         PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 313         /* GPP_H08:     UART0_BUF_RXD */
 314         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 315         /* GPP_H09:     UART0_BUF_TXD */
 316         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 317         /* GPP_H10:     HW_ID6 */
 318         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
 319         /* GPP_H11:     NC */
 320         PAD_NC(GPP_H11, NONE),
 321         /* GPP_H13:     CPU_C10_GATE_N */
 322         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 323         /* GPP_H14:     AUTOOPEN_ALS_I2C_SDA */
 324         PAD_CFG_NF(GPP_H14, NONE, DEEP, NF3),
 325         /* GPP_H15:     AUTOOPEN_ALS_I2C_SCL */
 326         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF3),
 327         /* GPP_H16:     NC */
 328         PAD_NC(GPP_H16, NONE),
 329         /* GPP_H17:     SOC_SCI_N */
 330         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 331         /* GPP_H19:     HW_ID3 */
 332         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
 333         /* GPP_H20:     HW_ID2 */
 334         PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
 335         /* GPP_H21:     PCH_I2C_GSC_SDA */
 336         PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 337         /* GPP_H22:     PCH_I2C_GSC_SCL */
 338         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 339
 340         /* GPP_S00:     SNDW3_CLK_CODEC */
 341         PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
 342         /* GPP_S01:     SNDW3_DATA0_CODEC */
 343         PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
 344         /* GPP_S02:     SNDW3_DATA1_CODEC */
 345         PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
 346         /* GPP_S03:     SNDW3_DATA2_CODEC */
 347         PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
 348         /* GPP_S04:     SNDW2_CLK */
 349         PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
 350         /* GPP_S05:     SNDW2_DATA0 */
 351         PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
 352         /* GPP_S06:     SWIRE_AMP_CLK */
 353         PAD_NC(GPP_S06, NONE),
 354         /* GPP_S07:     SWIRE_AMP_DATA0 */
 355         PAD_NC(GPP_S07, NONE),
 356
 357         /* GPP_V00:     PM_BATLOW_N */
 358         PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 359         /* GPP_V01:     BC_ACOK_MCP */
 360         PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
 361         /* GPP_V02:     NC */
 362         PAD_NC(GPP_V02, NONE),
 363         /* GPP_V03:     PWRBTN_MCP_N */
 364         PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 365         /* GPP_V04:     PM_SLP_S3_N */
 366         PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 367         /* GPP_V05:     PM_SLP_S4_N */
 368         PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 369         /* GPP_V06:     NC */
 370         PAD_NC(GPP_V06, NONE),
 371         /* GPP_V07:     Not used */
 372         PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
 373         /* GPP_V08:     SLP_WLAN_N */
 374         PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 375         /* GPP_V09:     NC */
 376         PAD_NC(GPP_V09, NONE),
 377         /* GPP_V10:     NC */
 378         PAD_NC(GPP_V10, NONE),
 379         /* GPP_V11:     NC */
 380         PAD_NC(GPP_V11, NONE),
 381         /* GPP_V12:     NC */
 382         PAD_NC(GPP_V12, NONE),
 383         /* GPP_V13:     NC */
 384         PAD_NC(GPP_V13, NONE),
 385         /* GPP_V14:     NC */
 386         PAD_NC(GPP_V14, NONE),
 387         /* GPP_V15:     NC */
 388         PAD_NC(GPP_V15, NONE),
 389         /* GPP_V16:     VCCST_EN */
 390         PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
 391         /* GPP_V17:     GPP_V17 */
 392         PAD_NC(GPP_V17, NONE),
 393 };
 394
 395 /* Early pad configuration in bootblock */
 396 static const struct pad_config early_gpio_table[] = {
 397         /* GPP_H08:     UART0_BUF_RXD */
 398         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 399         /* GPP_H09:     UART0_BUF_TXD */
 400         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 401
 402         /* GPP_H06: I2C3_SDA_PSS */
 403         PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 404         /* GPP_H07: I2C3_SCL_PSS */
 405         PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 406         /* GPP_D15: SPI_TPM_INT_N */
 407         PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
 408 };
 409
 410 /* Pad configuration in romstage */
 411 static const struct pad_config romstage_gpio_table[] = {
 412         /* GPP_C03:     GPP_C0_SMBCLK */
 413         PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
 414         /* GPP_C04:     GPP_C0_SMBDATA */
 415         PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
 416 };
 417
 418 const struct pad_config *variant_gpio_table(size_t *num)
 419 {
 420         *num = ARRAY_SIZE(gpio_table);
 421         return gpio_table;
 422 }
 423
 424 const struct pad_config *variant_early_gpio_table(size_t *num)
 425 {
 426         *num = ARRAY_SIZE(early_gpio_table);
 427         return early_gpio_table;
 428 }
 429
 430 /* Create the stub for romstage gpio, typically use for power sequence */
 431 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 432 {
 433         *num = ARRAY_SIZE(romstage_gpio_table);
 434         return romstage_gpio_table;
 435 }
 436
 437 static const struct cros_gpio cros_gpios[] = {
 438         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
 439         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 440         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 441         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
 442 };
 443
 444 DECLARE_CROS_GPIOS(cros_gpios);