src/mainboard/google/fizz/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <baseboard/variants.h>
   5 #include <bootmode.h>
   6 #include <chip.h>
   7 #include <console/console.h>
   8 #include <delay.h>
   9 #include <device/device.h>
  10 #include <ec/ec.h>
  11 #include <ec/google/chromeec/ec.h>
  12 #include <gpio.h>
  13 #include <intelblocks/power_limit.h>
  14 #include <smbios.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/nhlt.h>
  17 #include <static.h>
  18 #include <stdio.h>
  19 #include <timer.h>
  20
  21 #include <variant/gpio.h>
  22
  23 #define FIZZ_SKU_ID_I7_U42  0x4
  24 #define FIZZ_SKU_ID_I5_U42  0x5
  25 #define FIZZ_SKU_ID_I3_U42  0x6
  26 #define FIZZ_SKU_ID_I7_U22  0x3
  27 #define FIZZ_SKU_ID_I5_U22  0x2
  28 #define FIZZ_SKU_ID_I3_U22  0x1
  29 #define FIZZ_SKU_ID_CEL_U22 0x0
  30 #define FIZZ_PL2_U42        44
  31 #define FIZZ_PL2_U22        29
  32 #define FIZZ_PSYSPL2_U22    65
  33 #define FIZZ_PSYSPL2_U42    90
  34 #define FIZZ_MAX_TIME_WINDOW 6
  35 #define FIZZ_MIN_DUTYCYCLE   4
  36 /*
  37  * For type-C chargers, set PL2 to 90% of max power to account for
  38  * cable loss and FET Rdson loss in the path from the source.
  39  */
  40 #define SET_PSYSPL2(w)     (9 * (w) / 10)
  41
  42 static uint8_t read_sku_id_from_gpio(void)
  43 {
  44         const gpio_t sku_id_gpios[] = {
  45                 GPIO_SKU_ID0,
  46                 GPIO_SKU_ID1,
  47                 GPIO_SKU_ID2,
  48                 GPIO_SKU_ID3,
  49         };
  50         return gpio_base2_value(sku_id_gpios, ARRAY_SIZE(sku_id_gpios));
  51 }
  52
  53 static uint8_t board_sku_id(void)
  54 {
  55         static int sku_id = -1;
  56
  57         if (sku_id < 0) {
  58                 uint32_t id;
  59                 if (google_chromeec_cbi_get_sku_id(&id))
  60                         /* TODO: Once transition completes, raise error instead
  61                            of returning gpio value which could be unintended. */
  62                         /* Reading from EC may succeed next time but we do not
  63                            want to return different values. So, we cache the
  64                            value read from GPIOs. */
  65                         id = read_sku_id_from_gpio();
  66                 sku_id = id;
  67         }
  68
  69         return sku_id;
  70 }
  71
  72 /*
  73  * mainboard_set_power_limits
  74  *
  75  * Set Pl2 and SysPl2 values based on detected charger.
  76  * If detected barrel jack, use values below based on SKU.
  77  * definitions:
  78  * x = no value entered. Use default value in parenthesis.
  79  *     will set 0 to anything that shouldn't be set.
  80  * n = max value of power adapter.
  81  * +-------------+-----+---------+-----------+-------+
  82  * | sku_id      | PL2 | PsysPL2 |  PsysPL3  |  PL4  |
  83  * +-------------+-----+---------+-----------+-------+
  84  * | i7 U42      |  44 |   81    | x(.85PL4) | x(71) |
  85  * | i5 U42      |  44 |   81    | x(.85PL4) | x(71) |
  86  * | i3 U42      |  44 |   81    | x(.85PL4) | x(71) |
  87  * | i7 U22      |  29 |   58    | x(.85PL4) | x(43) |
  88  * | i5 U22      |  29 |   58    | x(.85PL4) | x(43) |
  89  * | i3 U22      |  29 |   58    | x(.85PL4) | x(43) |
  90  * | celeron U22 |  29 |   58    | x(.85PL4) | x(43) |
  91  * +-------------+-----+---------+-----------+-------+
  92  * For USB C charger:
  93  * +-------------+-----+---------+---------+-------+
  94  * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 |  PL4  |
  95  * +-------------+-----+---------+---------+-------+
  96  * | 60 (U42)    |  44 |   54    |    54   |   54  |
  97  * | 60 (U22)    |  29 |   54    |    54   | x(43) |
  98  * | n  (U42)    |  44 |   .9n   |   .9n   |  .9n  |
  99  * | n  (U22)    |  29 |   .9n   |   .9n   | x(43) |
 100  * +-------------+-----+---------+---------+-------+
 101  */
 102 static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
 103 {
 104         enum usb_chg_type type;
 105         u32 watts;
 106         u16 volts_mv, current_ma;
 107         u32 pl2, psyspl2;
 108         int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
 109         uint8_t sku = board_sku_id();
 110         const uint32_t u42_mask = (1 << FIZZ_SKU_ID_I7_U42) |
 111                                   (1 << FIZZ_SKU_ID_I5_U42) |
 112                                   (1 << FIZZ_SKU_ID_I3_U42);
 113
 114         /* PL2 value is sku-based, no matter what charger we are using */
 115         pl2 = FIZZ_PL2_U22;
 116         if ((1 << sku) & u42_mask)
 117                 pl2 = FIZZ_PL2_U42;
 118         conf->tdp_psyspl3 = conf->tdp_pl4 = 0;
 119
 120         /* If we can't get charger info or not PD charger, assume barrel jack */
 121         if (rv != 0 || type != USB_CHG_TYPE_PD) {
 122                 /* using the barrel jack, get PsysPL2 based on sku id */
 123                 psyspl2 = FIZZ_PSYSPL2_U22;
 124                 /* Running a U42 SKU */
 125                 if ((1 << sku) & u42_mask)
 126                         psyspl2 = FIZZ_PSYSPL2_U42;
 127         } else {
 128                 /* Detected TypeC.  Base on max value of adapter */
 129                 watts = ((u32)volts_mv * current_ma) / 1000000;
 130                 psyspl2 = watts;
 131                 conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
 132                 /* set max possible time window */
 133                 conf->tdp_psyspl3_time = FIZZ_MAX_TIME_WINDOW;
 134                 /* set minimum duty cycle */
 135                 conf->tdp_psyspl3_dutycycle = FIZZ_MIN_DUTYCYCLE;
 136                 if ((1 << sku) & u42_mask)
 137                         conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
 138         }
 139
 140         conf->tdp_pl2_override = pl2;
 141         /* set psyspl2 to 90% of max adapter power */
 142         conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
 143 }
 144
 145 static uint8_t read_oem_id_from_gpio(void)
 146 {
 147         const gpio_t oem_id_gpios[] = {
 148                 GPIO_OEM_ID1,
 149                 GPIO_OEM_ID2,
 150                 GPIO_OEM_ID3,
 151         };
 152         return gpio_base2_value(oem_id_gpios, ARRAY_SIZE(oem_id_gpios));
 153 }
 154
 155 static uint8_t board_oem_id(void)
 156 {
 157         static int oem_id = -1;
 158
 159         if (oem_id < 0) {
 160                 uint32_t id;
 161                 if (google_chromeec_cbi_get_oem_id(&id))
 162                         /* TODO: Once transition completes, raise error instead
 163                            of returning gpio value which could be unintended. */
 164                         /* Reading from EC may succeed next time but we do not
 165                            want to return different values. So, we cache the
 166                            value read from GPIOs. */
 167                         id = read_oem_id_from_gpio();
 168                 oem_id = id;
 169         }
 170
 171         return oem_id;
 172 }
 173
 174 const char *smbios_system_sku(void)
 175 {
 176         static char sku_str[7]; /* sku{0..255} */
 177
 178         snprintf(sku_str, sizeof(sku_str), "sku%d", board_oem_id());
 179
 180         return sku_str;
 181 }
 182
 183 const char *fizz_oem_name[] = {
 184         "Kench",
 185         "Teemo",
 186         "Sion",
 187         "Wukong",
 188         "Wukong",
 189         "Wukong",
 190         "Teemo",
 191         "Karma",
 192         "Jax",
 193         "Endeavour",
 194         "Excelsior"
 195 };
 196
 197 const char *smbios_mainboard_product_name(void)
 198 {
 199         return fizz_oem_name[board_oem_id()];
 200 }
 201
 202 static void mainboard_init(struct device *dev)
 203 {
 204         mainboard_ec_init();
 205 }
 206
 207 static unsigned long mainboard_write_acpi_tables(
 208         const struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
 209 {
 210         const char *oem_id = NULL;
 211         const char *oem_table_id = NULL;
 212         uint32_t oem_revision = 0;
 213         uintptr_t start_addr;
 214         uintptr_t end_addr;
 215         struct nhlt *nhlt;
 216
 217         start_addr = current;
 218
 219         nhlt = nhlt_init();
 220         if (!nhlt)
 221                 return start_addr;
 222
 223         variant_nhlt_init(nhlt);
 224         variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision);
 225
 226         end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
 227                                 oem_id, oem_table_id, oem_revision);
 228
 229         if (end_addr != start_addr)
 230                 acpi_add_table(rsdp, (void *)start_addr);
 231
 232         return end_addr;
 233 }
 234
 235 static void mainboard_enable(struct device *dev)
 236 {
 237         struct soc_power_limits_config *soc_conf;
 238         config_t *conf = config_of_soc();
 239
 240         soc_conf = &conf->power_limits_config;
 241         mainboard_set_power_limits(soc_conf);
 242
 243         dev->ops->init = mainboard_init;
 244         dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 245 }
 246
 247 #define GPIO_HDMI_HPD           GPP_E13
 248 #define GPIO_DP_HPD             GPP_E14
 249
 250 /* TODO: This can be moved to common directory */
 251 static void wait_for_hpd(gpio_t gpio, long timeout)
 252 {
 253         struct stopwatch sw;
 254
 255         printk(BIOS_INFO, "Waiting for HPD\n");
 256         gpio_input(gpio);
 257
 258         stopwatch_init_msecs_expire(&sw, timeout);
 259         while (!gpio_get(gpio)) {
 260                 if (stopwatch_expired(&sw)) {
 261                         printk(BIOS_WARNING,
 262                                "HPD not ready after %ldms. Abort.\n", timeout);
 263                         return;
 264                 }
 265                 mdelay(200);
 266         }
 267         printk(BIOS_INFO, "HPD ready after %lld ms\n",
 268                stopwatch_duration_msecs(&sw));
 269 }
 270
 271 void __weak variant_chip_display_init(void)
 272 {
 273         static const long display_timeout_ms = 3000;
 274
 275         /* This is reconfigured back to whatever FSP-S expects by
 276            gpio_configure_pads. */
 277         gpio_input(GPIO_HDMI_HPD);
 278         if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) {
 279                 /* This has to be done before FSP-S runs. */
 280                 if (google_chromeec_wait_for_displayport(display_timeout_ms))
 281                         wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
 282         }
 283 }
 284
 285 static void mainboard_chip_init(void *chip_info)
 286 {
 287         const struct pad_config *pads;
 288         size_t num;
 289
 290         variant_chip_display_init();
 291
 292         pads = variant_gpio_table(&num);
 293         gpio_configure_pads(pads, num);
 294 }
 295
 296 struct chip_operations mainboard_ops = {
 297         .init = mainboard_chip_init,
 298         .enable_dev = mainboard_enable,
 299 };