?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
[coreboot2.git] / src / mainboard / intel / adlrvp / devicetree.cb
bloba3b3c93235b53d0f296fc2c3d344faa87571b684
1 chip soc/intel/alderlake
2
3 # This disables autonomous GPIO power management, otherwise
4 # old cr50 FW only supports short pulses.
5 register "gpio_override_pm" = "1"
6 register "gpio_pm[COMM_0]" = "0"
7 register "gpio_pm[COMM_1]" = "0"
8 register "gpio_pm[COMM_2]" = "0"
9 register "gpio_pm[COMM_4]" = "0"
10 register "gpio_pm[COMM_5]" = "0"
11
12 # GPE configuration
13 # Note that GPE events called out in ASL code rely on this
14 # route. i.e. If this route changes then the affected GPE
15 # offset bits also need to be changed.
16 register "pmc_gpe0_dw0" = "GPP_B"
17 register "pmc_gpe0_dw1" = "GPP_D"
18 register "pmc_gpe0_dw2" = "GPP_E"
19
20 # FSP configuration
21
22 # Enable CNVi BT
23 register "cnvi_bt_core" = "true"
24
25 # Sagv Configuration
26 register "sagv" = "SaGv_Enabled"
27
28 register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
29 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
30 register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3
31 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
32 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4
33 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
34 register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
35 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
36 register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
37 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
38
39 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
40 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
41 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
42 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
43
44 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
45 register "gen1_dec" = "0x00fc0801"
46 register "gen2_dec" = "0x000c0201"
47 # EC memory map range is 0x900-0x9ff
48 register "gen3_dec" = "0x00fc0901"
49
50 # Enable PCH PCIE RP 5 using CLK 2
51 register "pch_pcie_rp[PCH_RP(5)]" = "{
52 .clk_src = 2,
53 .clk_req = 2,
54 .flags = PCIE_RP_CLK_REQ_DETECT,
55 }"
56
57 # Enable PCH PCIE RP 6 using CLK 5
58 register "pch_pcie_rp[PCH_RP(6)]" = "{
59 .clk_src = 5,
60 .clk_req = 5,
61 .flags = PCIE_RP_CLK_REQ_DETECT,
62 }"
63
64 # NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
65 register "pch_pcie_rp[PCH_RP(8)]" = "{
66 .clk_src = 7,
67 .clk_req = 7,
68 .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
69 .PcieRpL1Substates = L1_SS_L1_2,
70 .pcie_rp_detect_timeout_ms = 50,
71 }"
72
73 # Enable PCH PCIE RP 9 using CLK 1
74 register "pch_pcie_rp[PCH_RP(9)]" = "{
75 .clk_src = 1,
76 .clk_req = 1,
77 .flags = PCIE_RP_CLK_REQ_DETECT,
78 }"
79
80 # Enable PCH PCIE RP 11 for optane
81 register "pch_pcie_rp[PCH_RP(11)]" = "{
82 .flags = PCIE_RP_CLK_SRC_UNUSED,
83 }"
84
85 # Hybrid storage mode
86 register "hybrid_storage_mode" = "true"
87
88 # Enable CPU PCIE RP 1 using CLK 0
89 register "cpu_pcie_rp[CPU_RP(1)]" = "{
90 .clk_req = 0,
91 .clk_src = 0,
92 .flags = PCIE_RP_LTR | PCIE_RP_AER,
93 }"
94
95 # Enable CPU PCIE RP 2 using CLK 3
96 register "cpu_pcie_rp[CPU_RP(2)]" = "{
97 .clk_req = 3,
98 .clk_src = 3,
99 .flags = PCIE_RP_LTR | PCIE_RP_AER,
100 }"
101
102 # Enable CPU PCIE RP 3 using CLK 4
103 register "cpu_pcie_rp[CPU_RP(3)]" = "{
104 .clk_req = 4,
105 .clk_src = 4,
106 .flags = PCIE_RP_LTR | PCIE_RP_AER,
107 }"
108
109 register "sata_salp_support" = "1"
110
111 register "sata_ports_enable" = "{
112 [0] = 1,
113 [1] = 1,
114 [2] = 1,
115 [3] = 1,
116 }"
117
118 register "sata_ports_dev_slp" = "{
119 [0] = 1,
120 [1] = 1,
121 [2] = 1,
122 [3] = 1,
123 }"
124
125 # Enable EDP in PortA
126 register "ddi_portA_config" = "1"
127 # Enable HDMI in Port B
128 register "ddi_ports_config" = "{
129 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
130 }"
131
132 # TCSS USB3
133 register "tcss_aux_ori" = "0"
134
135 register "s0ix_enable" = "true"
136 register "dptf_enable" = "1"
137
138 register "serial_io_i2c_mode" = "{
139 [PchSerialIoIndexI2C0] = PchSerialIoPci,
140 [PchSerialIoIndexI2C1] = PchSerialIoPci,
141 [PchSerialIoIndexI2C2] = PchSerialIoPci,
142 [PchSerialIoIndexI2C3] = PchSerialIoPci,
143 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
144 [PchSerialIoIndexI2C5] = PchSerialIoPci,
145 }"
146
147 register "serial_io_gspi_mode" = "{
148 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
149 [PchSerialIoIndexGSPI1] = PchSerialIoPci,
150 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
151 [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
152 }"
153
154 register "serial_io_gspi_cs_mode" = "{
155 [PchSerialIoIndexGSPI0] = 0,
156 [PchSerialIoIndexGSPI1] = 1,
157 [PchSerialIoIndexGSPI2] = 0,
158 [PchSerialIoIndexGSPI3] = 0,
159 }"
160
161 register "serial_io_gspi_cs_state" = "{
162 [PchSerialIoIndexGSPI0] = 0,
163 [PchSerialIoIndexGSPI1] = 0,
164 [PchSerialIoIndexGSPI2] = 0,
165 [PchSerialIoIndexGSPI3] = 0,
166 }"
167
168 register "serial_io_uart_mode" = "{
169 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
170 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
171 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
172 }"
173
174 # HD Audio
175 register "pch_hda_dsp_enable" = "1"
176 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
177 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
178 register "pch_hda_idisp_codec_enable" = "1"
179
180 register "cnvi_bt_audio_offload" = "true"
181
182 # Intel Common SoC Config
183 register "common_soc_config" = "{
184 .gspi[1] = {
185 .speed_mhz = 1,
186 .early_init = 1,
187 },
188 .i2c[0] = {
189 .speed = I2C_SPEED_FAST,
190 },
191 .i2c[1] = {
192 .speed = I2C_SPEED_FAST,
193 },
194 .i2c[2] = {
195 .speed = I2C_SPEED_FAST,
196 },
197 .i2c[3] = {
198 .speed = I2C_SPEED_FAST,
199 },
200 .i2c[5] = {
201 .speed = I2C_SPEED_FAST,
202 },
203 }"
204
205 device domain 0 on
206 device ref pcie5_0 on end
207 device ref igpu on end
208 device ref dtt on
209 chip drivers/intel/dptf
210
211 ## sensor information
212 register "options.tsr[0].desc" = ""Ambient""
213 register "options.tsr[1].desc" = ""Battery""
214 register "options.tsr[2].desc" = ""DDR""
215 register "options.tsr[3].desc" = ""Skin""
216
217 ## Active Policy
218 # TODO: below values are initial reference values only
219 register "policies.active" = "{
220 [0] = {
221 .target = DPTF_CPU,
222 .thresholds = {
223 TEMP_PCT(95, 90),
224 TEMP_PCT(90, 80),
225 }
226 },
227 [1] = {
228 .target = DPTF_TEMP_SENSOR_0,
229 .thresholds = {
230 TEMP_PCT(80, 90),
231 TEMP_PCT(70, 80),
232 }
233 }
234 }"
235
236 ## Passive Policy
237 # TODO: below values are initial reference values only
238 register "policies.passive" = "{
239 [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
240 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
241 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
242 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
243 [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
244 }"
245
246 ## Critical Policy
247 # TODO: below values are initial reference values only
248 register "policies.critical" = "{
249 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
250 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
251 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
252 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
253 [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
254 }"
255
256 ## Power Limits Control
257 register "controls.power_limits" = "{
258 .pl1 = {
259 .min_power = 35000,
260 .max_power = 45000,
261 .time_window_min = 28 * MSECS_PER_SEC,
262 .time_window_max = 32 * MSECS_PER_SEC,
263 .granularity = 200,
264 },
265 .pl2 = {
266 .min_power = 56000,
267 .max_power = 56000,
268 .time_window_min = 28 * MSECS_PER_SEC,
269 .time_window_max = 32 * MSECS_PER_SEC,
270 .granularity = 1000,
271 }
272 }"
273
274 ## Charger Performance Control (Control, mA)
275 register "controls.charger_perf" = "{
276 [0] = { 255, 3000 },
277 [1] = { 24, 1500 },
278 [2] = { 16, 1000 },
279 [3] = { 8, 500 }
280 }"
281
282 ## Fan Performance Control (Percent, Speed, Noise, Power)
283 register "controls.fan_perf" = "{
284 [0] = { 90, 6700, 220, 2200, },
285 [1] = { 80, 5800, 180, 1800, },
286 [2] = { 70, 5000, 145, 1450, },
287 [3] = { 60, 4900, 115, 1150, },
288 [4] = { 50, 3838, 90, 900, },
289 [5] = { 40, 2904, 55, 550, },
290 [6] = { 30, 2337, 30, 300, },
291 [7] = { 20, 1608, 15, 150, },
292 [8] = { 10, 800, 10, 100, },
293 [9] = { 0, 0, 0, 50, }
294 }"
295
296 ## Fan options
297 register "options.fan.fine_grained_control" = "1"
298 register "options.fan.step_size" = "2"
299
300 device generic 0 alias dptf_policy on end
301 end
302 end
303 device ref ipu on
304 chip drivers/intel/mipi_camera
305 register "acpi_uid" = "0x50000"
306 register "acpi_name" = ""IPU0""
307 register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
308
309 register "cio2_num_ports" = "2"
310 register "cio2_lanes_used" = "{2,2}"
311 register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
312 register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
313 register "cio2_prt[0]" = "2"
314 register "cio2_prt[1]" = "1"
315 device generic 0 on end
316 end
317 end
318 device ref pcie4_0 on end
319 device ref pcie4_1 on end
320 device ref tbt_pcie_rp0 on end
321 device ref tbt_pcie_rp1 on end
322 device ref tbt_pcie_rp2 on end
323 device ref tbt_pcie_rp3 on end
324 device ref crashlog off end
325 device ref tcss_xhci on end
326 device ref tcss_dma0 on end
327 device ref tcss_dma1 on end
328 device ref xhci on
329 chip drivers/usb/acpi
330 register "desc" = ""Root Hub""
331 register "type" = "UPC_TYPE_HUB"
332 device ref xhci_root_hub on
333 chip drivers/usb/acpi
334 register "desc" = ""Bluetooth""
335 register "type" = "UPC_TYPE_INTERNAL"
336 device ref usb2_port10 on end
337 end
338 end
339 end
340 end
341 device ref cnvi_wifi on
342 chip drivers/wifi/generic
343 register "wake" = "GPE0_PME_B0"
344 device generic 0 on end
345 end
346 end
347 device ref i2c0 on end
348 device ref i2c1 on
349 chip drivers/intel/mipi_camera
350 register "acpi_hid" = ""OVTI5675""
351 register "acpi_uid" = "0"
352 register "acpi_name" = ""CAM0""
353 register "chip_name" = ""Ov 5675 Camera""
354 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
355
356 register "ssdb.lanes_used" = "2"
357 register "ssdb.vcm_type" = "0x0C"
358 register "vcm_name" = ""VCM0""
359 register "num_freq_entries" = "1"
360 register "link_freq[0]" = "450000000"
361 register "remote_name" = ""IPU0""
362
363 register "has_power_resource" = "1"
364 #Controls
365 register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
366 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
367 register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
368 register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
369
370 #_ON
371 register "on_seq.ops_cnt" = "4"
372 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
373 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
374 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
375 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
376
377 #_OFF
378 register "off_seq.ops_cnt" = "3"
379 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
380 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
381 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
382
383 device i2c 36 on end
384 end
385 chip drivers/intel/mipi_camera
386 register "acpi_uid" = "3"
387 register "acpi_name" = ""VCM0""
388 register "chip_name" = ""DW AF VCM""
389 register "device_type" = "INTEL_ACPI_CAMERA_VCM"
390
391 register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
392 register "vcm_compat" = ""dongwoon,dw9714""
393
394 device i2c 0C on end
395 end
396 end
397 device ref i2c2 on end
398 device ref i2c3 on end
399 device ref heci1 on end
400 device ref sata on end
401 device ref i2c5 on
402 chip drivers/intel/mipi_camera
403 register "acpi_hid" = ""OVTI5675""
404 register "acpi_uid" = "0"
405 register "acpi_name" = ""CAM1""
406 register "chip_name" = ""Ov 5675 Camera""
407 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
408
409 register "ssdb.lanes_used" = "2"
410 register "num_freq_entries" = "1"
411 register "link_freq[0]" = "450000000"
412 register "remote_name" = ""IPU0""
413
414 register "has_power_resource" = "1"
415 #Controls
416 register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
417 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
418 register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
419 register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
420
421 #_ON
422 register "on_seq.ops_cnt" = "4"
423 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
424 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
425 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
426 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
427
428 #_OFF
429 register "off_seq.ops_cnt" = "3"
430 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
431 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
432 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
433
434 device i2c 36 on end
435 end
436 end
437 device ref pcie_rp5 on end
438 device ref pcie_rp6 on end
439 device ref pcie_rp8 on end
440 device ref pcie_rp9 on end
441 device ref pcie_rp11 on end
442 device ref uart0 on end
443 device ref gspi0 on end
444 device ref p2sb on end
445 device ref gspi1 on
446 chip drivers/spi/acpi
447 register "hid" = "ACPI_DT_NAMESPACE_HID"
448 register "compat_string" = ""google,cr50""
449 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
450 device spi 0 on end
451 end
452 end
453 device ref hda on
454 chip drivers/intel/soundwire
455 device generic 0 on
456 chip drivers/soundwire/alc711
457 # SoundWire Link 0 ID 1
458 register "desc" = ""Headset Codec""
459 register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
460 register "alc711_address.class" = "MIPI_CLASS_NONE"
461 register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
462 device generic 0.1 on end
463 end
464 end
465 end
466 end
467 device ref smbus on end
468 end
469 end
coreboot repo mirror