src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef _SKXSP_TP_IIO_H_
   4 #define _SKXSP_TP_IIO_H_
   5
   6 #include <FspmUpd.h>
   7 #include <soc/pci_devs.h>
   8
   9 enum tp_iio_bifur_table_index {
  10         Skt0_Iou0 = 0,
  11         Skt0_Iou1,
  12         Skt0_Iou2,
  13         Skt0_Mcp0,
  14         Skt0_Mcp1,
  15         Skt1_Iou0,
  16         Skt1_Iou1,
  17         Skt1_Iou2,
  18         Skt1_Mcp0,
  19         Skt1_Mcp1
  20 };
  21
  22 /*
  23  * Standard Tioga Pass Iio Bifurcation Table
  24  * This is SS 2x16 config. As documented in OCP TP spec, there are
  25  * 3 configs. SS 2x16 is the most common.
  26  * TODO: figure out config through board SKU ID and through PCIe
  27  * config GPIO setting (SLT_CFG0 / SLT_CFG1).
  28  */
  29 static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
  30         { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */
  31         { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */
  32         { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */
  33         { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  34         { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  35         { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */
  36         { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */
  37         { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */
  38         { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  39         { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  40 };
  41
  42 #define CFG_UPD_PORT(port, hide)                                \
  43         {                                                       \
  44                 .PortIndex           = port,                    \
  45                 .HidePort            = hide,                    \
  46                 .DeEmphasis          = 0x00,                    \
  47                 .PortLinkSpeed       = PcieAuto,                \
  48                 .MaxPayload          = 0x00,                    \
  49                 .DfxDnTxPreset       = 0xFF,                    \
  50                 .DfxRxPreset         = 0xFF,                    \
  51                 .DfxUpTxPreset       = 0xFF,                    \
  52                 .Sris                = 0x00,                    \
  53                 .PcieCommonClock     = 0x00,                    \
  54                 .NtbPpd              = NTB_PORT_TRANSPARENT,    \
  55                 .NtbSplitBar         = 0x00,                    \
  56                 .NtbBarSizePBar23    = 0x16,                    \
  57                 .NtbBarSizePBar4     = 0x16,                    \
  58                 .NtbBarSizePBar5     = 0x16,                    \
  59                 .NtbBarSizePBar45    = 0x16,                    \
  60                 .NtbBarSizeSBar23    = 0x16,                    \
  61                 .NtbBarSizeSBar4     = 0x16,                    \
  62                 .NtbBarSizeSBar5     = 0x16,                    \
  63                 .NtbBarSizeSBar45    = 0x16,                    \
  64                 .NtbSBar01Prefetch   = 0x00,                    \
  65                 .NtbXlinkCtlOverride = 0x03,                    \
  66         }
  67
  68 /*
  69  * Standard Tioga Pass Iio PCIe Port Table
  70  */
  71 static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
  72         CFG_UPD_PORT(PORT_1A, NOT_HIDE),
  73         CFG_UPD_PORT(PORT_1B, HIDE),
  74         CFG_UPD_PORT(PORT_1C, HIDE),
  75         CFG_UPD_PORT(PORT_1D, HIDE),
  76         CFG_UPD_PORT(PORT_2A, NOT_HIDE),
  77         CFG_UPD_PORT(PORT_2B, HIDE),
  78         CFG_UPD_PORT(PORT_2C, HIDE),
  79         CFG_UPD_PORT(PORT_2D, HIDE),
  80         CFG_UPD_PORT(PORT_3A, NOT_HIDE),
  81         CFG_UPD_PORT(PORT_3B, HIDE),
  82         CFG_UPD_PORT(PORT_3C, NOT_HIDE),
  83         CFG_UPD_PORT(PORT_3D, HIDE),
  84 };
  85
  86 /*
  87  * Standard Tioga Pass PCH PCIe Port Table
  88  */
  89 static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = {
  90         //PortIndex ; ForceEnable ; PortLinkSpeed
  91         { 0x00, 0x00, PcieAuto },
  92         { 0x04, 0x00, PcieAuto },
  93         { 0x05, 0x00, PcieAuto },
  94 };
  95
  96 #endif /* _SKXSP_TP_IIO_H_ */