src/mainboard/protectli/vault_cml/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <soc/gpio.h>
   5 #include <superio/ite/common/ite.h>
   6 #include <superio/ite/it8784e/it8784e.h>
   7 #include "gpio.h"
   8
   9 #define UART_DEV PNP_DEV(0x2e, IT8784E_SP1)
  10 #define GPIO_DEV PNP_DEV(0x2e, IT8784E_GPIO)
  11
  12 void bootblock_mainboard_early_init(void)
  13 {
  14         /* CLKIN freq 24MHz, Ext CLKIN for Watchdog, Internal VCC_OK */
  15         ite_reg_write(GPIO_DEV, 0x23, 0x49);
  16         /* Set pin native functions */
  17         ite_reg_write(GPIO_DEV, 0x26, 0xf3);
  18         /* Set GPIOS exposed on pin header as GPIO functions  */
  19         ite_reg_write(GPIO_DEV, 0x29, 0xc0);
  20         /* External CLKIN PCICLK */
  21         ite_reg_write(GPIO_DEV, 0x71, 0x08);
  22         /* Enable 3VSB during Suspend-to-RAM */
  23         ite_enable_3vsbsw(GPIO_DEV);
  24         /* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */
  25         ite_delay_pwrgd3(GPIO_DEV);
  26         ite_kill_watchdog(GPIO_DEV);
  27         ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
  28 }
  29
  30 void bootblock_mainboard_init(void)
  31 {
  32         const struct pad_config *pads;
  33         size_t num;
  34
  35         pads = board_gpio_table(&num);
  36         gpio_configure_pads(pads, num);
  37 }