src/northbridge/intel/e7505/e7505.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * e7505.h: PCI configuration space for the Intel E7501 memory controller
   5  */
   6
   7 #ifndef NORTHBRIDGE_INTEL_E7505_E7505_H
   8 #define NORTHBRIDGE_INTEL_E7505_E7505_H
   9
  10 #include <types.h>
  11
  12 size_t northbridge_get_tseg_size(void);
  13 uintptr_t northbridge_get_tseg_base(void);
  14
  15 /************  D0:F0 ************/
  16 // Register offsets
  17 #define SMRBASE         0x14    /* System Memory RCOMP Base Address Register, 32 bit? */
  18 #define MCHCFGNS        0x52    /* MCH (scrubber) configuration register, 16 bit */
  19
  20 #define PAM_0           0x59
  21
  22 #define DRB_ROW_0       0x60    /* DRAM Row Boundary register, 8 bit */
  23 #define DRB_ROW_1       0x61
  24 #define DRB_ROW_2       0x62
  25 #define DRB_ROW_3       0x63
  26 #define DRB_ROW_4       0x64
  27 #define DRB_ROW_5       0x65
  28 #define DRB_ROW_6       0x66
  29 #define DRB_ROW_7       0x67
  30
  31 #define DRA             0x70    /* DRAM Row Attributes registers, 4 x 8 bit */
  32 #define DRT             0x78    /* DRAM Timing register, 32 bit */
  33 #define DRC             0x7C    /* DRAM Controller Mode register, 32 bit */
  34 #define DRDCTL          0x80    /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
  35 #define CKDIS           0x8C    /* Clock disable register, 8 bit */
  36 #define APSIZE          0xB4
  37 #define TOLM            0xC4    /* Top of Low Memory register, 16 bit */
  38 #define REMAPBASE       0xC6    /* Remap Base Address register, 16 bit */
  39 #define REMAPLIMIT      0xC8    /* Remap Limit Address register, 16 bit */
  40 #define SKPD            0xDE    /* Scratchpad register, 16 bit */
  41 #define DVNP            0xE0    /* Device Not Present, 16 bit */
  42 #define MCHTST          0xF4    /* MCH Test Register, 32 bit? (if similar to 855PM) */
  43
  44 #define SMRAMC          0x9D
  45 #define C_BASE_SEG      ((0 << 2) | (1 << 1) | (0 << 0))
  46 #define G_SMRAME        (1 << 3)
  47 #define D_LCK           (1 << 4)
  48 #define D_CLS           (1 << 5)
  49 #define D_OPEN          (1 << 6)
  50
  51 #define ESMRAMC         0x9E
  52 #define T_EN            (1 << 0)
  53 #define TSEG_SZ_128K    (0 << 1)
  54 #define TSEG_SZ_256K    (1 << 1)
  55 #define TSEG_SZ_512K    (2 << 1)
  56 #define TSEG_SZ_1M      (3 << 1)
  57 #define TSEG_SZ_MASK    TSEG_SZ_1M
  58 #define H_SMRAME        (1 << 7)
  59
  60 // CAS# Latency bits in the DRAM Timing (DRT) register
  61 #define DRT_CAS_2_5             (0<<4)
  62 #define DRT_CAS_2_0             (1<<4)
  63 #define DRT_CAS_MASK            (3<<4)
  64
  65 // Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register
  66 #define RAM_COMMAND_NOP         (1<<4)
  67 #define RAM_COMMAND_PRECHARGE   (2<<4)
  68 #define RAM_COMMAND_MRS         (3<<4)
  69 #define RAM_COMMAND_EMRS        (4<<4)
  70 #define RAM_COMMAND_CBR         (6<<4)
  71 #define RAM_COMMAND_NORMAL      (7<<4)
  72
  73 #define DRC_DONE                (1 << 29)
  74
  75 // RCOMP Memory Map offsets
  76 // Conjecture based on apparent similarity between E7501 and 855PM
  77 // Intel doc. 252613-003 describes these for 855PM
  78
  79 #define SMRCTL          0x20    /* System Memory RCOMP Control Register? */
  80 #define DQCMDSTR        0x30    /* Strength control for DQ and CMD signal groups? */
  81 #define CKESTR          0x31    /* Strength control for CKE signal group? */
  82 #define CSBSTR          0x32    /* Strength control for CS# signal group? */
  83 #define CKSTR           0x33    /* Strength control for CK signal group? */
  84 #define RCVENSTR        0x34    /* Strength control for RCVEnOut# signal group? */
  85
  86 /************  D0:F1 ************/
  87 // Register offsets
  88 #define FERR_GLOBAL     0x40    /* First global error register, 32 bits */
  89 #define NERR_GLOBAL     0x44    /* Next global error register, 32 bits */
  90 #define DRAM_FERR       0x80    /* DRAM first error register, 8 bits */
  91 #define DRAM_NERR       0x82    /* DRAM next error register, 8 bits */
  92
  93 /************  D1:F0 ************/
  94
  95 #define APSIZE1         0x74
  96
  97 #endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */