src/northbridge/intel/e7505/northbridge.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <console/console.h>
   5 #include <device/pci_ops.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <cpu/cpu.h>
   9 #include <cpu/x86/smm.h>
  10
  11 #include "e7505.h"
  12
  13 static void mch_domain_read_resources(struct device *dev)
  14 {
  15         int idx;
  16         uint64_t tom, remapbase, remaplimit;
  17         struct device *mc_dev;
  18
  19         pci_domain_read_resources(dev);
  20
  21         mc_dev = pcidev_on_root(0, 0);
  22         if (!mc_dev)
  23                 die("Could not find MCH device\n");
  24
  25         tom = pci_read_config8(mc_dev, DRB_ROW_7);
  26         tom <<= 26;
  27
  28         /* Remapped region with a 64 MiB granularity in register
  29            definition. Limit is inclusive, so add one. */
  30         remapbase = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff;
  31         remapbase <<= 26;
  32
  33         remaplimit = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff;
  34         remaplimit += 1;
  35         remaplimit <<= 26;
  36
  37         /* Report the memory regions */
  38         idx = 10;
  39         ram_range(dev, idx++, 0, 0xa0000);
  40         mmio_from_to(dev, idx++, 0xa0000, 0xc0000);
  41         ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
  42
  43         uintptr_t tseg_base;
  44         size_t tseg_size;
  45         smm_region(&tseg_base, &tseg_size);
  46         ram_from_to(dev, idx++, 1 * MiB, tseg_base);
  47         mmio_range(dev, idx++, tseg_base, tseg_size);
  48
  49         ASSERT(tom == remapbase);
  50         upper_ram_end(dev, idx++, remaplimit);
  51 }
  52
  53 static void mch_domain_set_resources(struct device *dev)
  54 {
  55         assign_resources(dev->downstream);
  56 }
  57
  58 struct device_operations e7505_pci_domain_ops = {
  59         .read_resources   = mch_domain_read_resources,
  60         .set_resources    = mch_domain_set_resources,
  61         .scan_bus         = pci_host_bridge_scan_bus,
  62         .ops_pci          = &pci_dev_ops_pci,
  63 };
  64
  65
  66 struct device_operations e7505_cpu_bus_ops = {
  67         .read_resources   = noop_read_resources,
  68         .set_resources    = noop_set_resources,
  69         .init             = mp_cpu_bus_init,
  70 };
  71
  72 struct chip_operations northbridge_intel_e7505_ops = {
  73         .name = "Intel E7505 Northbridge",
  74 };