src/soc/amd/phoenix/fsp_m_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* TODO: Update for Phoenix */
   4 /* TODO: See what can be moved to common */
   5
   6 #include <amdblocks/apob_cache.h>
   7 #include <amdblocks/ioapic.h>
   8 #include <amdblocks/memmap.h>
   9 #include <assert.h>
  10 #include <console/console.h>
  11 #include <console/uart.h>
  12 #include <device/device.h>
  13 #include <fsp/api.h>
  14 #include <soc/platform_descriptors.h>
  15 #include <soc/pci_devs.h>
  16 #include <static.h>
  17 #include <string.h>
  18 #include <types.h>
  19 #include <vendorcode/amd/fsp/phoenix/FspUsb.h>
  20 #include "chip.h"
  21
  22 __weak void mb_pre_fspm(FSP_M_CONFIG *mcfg)
  23 {
  24 }
  25
  26 static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg,
  27                         const fsp_dxio_descriptor *descs, size_t num)
  28 {
  29         size_t i;
  30
  31         ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT,
  32                         "Too many DXIO descriptors provided.");
  33
  34         for (i = 0; i < num; i++) {
  35                 memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0]));
  36         }
  37 }
  38
  39 static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg,
  40                         const fsp_ddi_descriptor *descs, size_t num)
  41 {
  42         size_t i;
  43
  44         ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT,
  45                         "Too many DDI descriptors provided.");
  46
  47         for (i = 0; i < num; i++) {
  48                 memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0]));
  49         }
  50 }
  51
  52 static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg)
  53 {
  54         const fsp_dxio_descriptor *fsp_dxio = NULL;
  55         const fsp_ddi_descriptor *fsp_ddi = NULL;
  56         size_t num_dxio = 0;
  57         size_t num_ddi = 0;
  58
  59         mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio,
  60                                                 &fsp_ddi, &num_ddi);
  61         fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio);
  62         fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi);
  63 }
  64
  65 static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg)
  66 {
  67         mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR;
  68         mcfg->gnb_ioapic_id = GNB_IOAPIC_ID;
  69         mcfg->fch_ioapic_id = FCH_IOAPIC_ID;
  70 }
  71
  72 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
  73 {
  74         FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
  75         const struct soc_amd_phoenix_config *config = config_of_soc();
  76
  77         mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
  78
  79         mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
  80         mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
  81         mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
  82         mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
  83         mcfg->serial_port_baudrate = get_uart_baudrate();
  84         mcfg->serial_port_refclk = uart_platform_refclk();
  85
  86         /* 0 is default */
  87         mcfg->ccx_down_core_mode = config->downcore_mode;
  88         mcfg->ccx_disable_smt = config->disable_smt;
  89
  90         /* when stt_control isn't 1, FSP will ignore the other stt values */
  91         mcfg->stt_control = config->stt_control;
  92         mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count;
  93         mcfg->stt_min_limit = config->stt_min_limit;
  94         mcfg->stt_m1 = config->stt_m1;
  95         mcfg->stt_m2 = config->stt_m2;
  96         mcfg->stt_m3 = config->stt_m3;
  97         mcfg->stt_m4 = config->stt_m4;
  98         mcfg->stt_m5 = config->stt_m5;
  99         mcfg->stt_m6 = config->stt_m6;
 100         mcfg->stt_c_apu = config->stt_c_apu;
 101         mcfg->stt_c_gpu = config->stt_c_gpu;
 102         mcfg->stt_c_hs2 = config->stt_c_hs2;
 103         mcfg->stt_alpha_apu = config->stt_alpha_apu;
 104         mcfg->stt_alpha_gpu = config->stt_alpha_gpu;
 105         mcfg->stt_alpha_hs2 = config->stt_alpha_hs2;
 106         mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu;
 107         mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu;
 108         mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2;
 109         mcfg->stt_error_coeff = config->stt_error_coeff;
 110         mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient;
 111
 112         /* all following fields being 0 is a valid config */
 113         mcfg->stapm_boost = config->stapm_boost;
 114         mcfg->stapm_time_constant = config->stapm_time_constant_s;
 115         mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit;
 116         mcfg->sustained_power_limit = config->sustained_power_limit_mW;
 117         mcfg->fast_ppt_limit = config->fast_ppt_limit_mW;
 118         mcfg->slow_ppt_limit = config->slow_ppt_limit_mW;
 119         mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s;
 120         mcfg->thermctl_limit = config->thermctl_limit_degreeC;
 121
 122         /* 0 is default */
 123         mcfg->smartshift_enable = config->smartshift_enable;
 124
 125         /* 0 is default */
 126         mcfg->system_configuration = config->system_configuration;
 127
 128         /* when cppc_ctrl is 0 the other values won't be used */
 129         mcfg->cppc_ctrl = config->cppc_ctrl;
 130         mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range;
 131         mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range;
 132         mcfg->cppc_epp_max_range = config->cppc_epp_max_range;
 133         mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
 134         mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
 135
 136         /* S0i3 enable */
 137         mcfg->s0i3_enable = config->s0ix_enable;
 138         mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN);
 139
 140         /* voltage regulator telemetry settings */
 141         mcfg->telemetry_vddcrvddfull_scale_current =
 142                 config->telemetry_vddcrvddfull_scale_current_mA;
 143         mcfg->telemetry_vddcrvddoffset =
 144                 config->telemetry_vddcrvddoffset;
 145         mcfg->telemetry_vddcrsocfull_scale_current =
 146                 config->telemetry_vddcrsocfull_scale_current_mA;
 147         mcfg->telemetry_vddcrsocOffset =
 148                 config->telemetry_vddcrsocoffset;
 149
 150         /* PCIe power vs. speed */
 151         mcfg->pspp_policy = config->pspp_policy;
 152
 153         mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda));
 154         mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda));
 155
 156         if (config->usb_phy_custom) {
 157                 /* devicetree config is const, use local copy */
 158                 static struct usb_phy_config lcl_usb_phy;
 159                 lcl_usb_phy = config->usb_phy;
 160                 lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION;
 161                 lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION;
 162                 lcl_usb_phy.TableLength = sizeof(struct usb_phy_config);
 163                 if ((uintptr_t)&lcl_usb_phy <= UINT32_MAX) {
 164                         mcfg->usb_phy_ptr = (uint32_t)(uintptr_t)&lcl_usb_phy;
 165                 } else {
 166                         printk(BIOS_ERR, "USB PHY config struct above 4GB; can't pass USB PHY "
 167                                          "configuration to 32 bit FSP.\n");
 168                         mcfg->usb_phy_ptr = 0;
 169                 }
 170         } else {
 171                 mcfg->usb_phy_ptr = 0;
 172         }
 173
 174         fsp_fill_pcie_ddi_descriptors(mcfg);
 175         fsp_assign_ioapic_upds(mcfg);
 176         mb_pre_fspm(mcfg);
 177 }