src/soc/amd/stoneyridge/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <assert.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/msr.h>
   7 #include <cpu/x86/mtrr.h>
   8 #include <smp/node.h>
   9 #include <bootblock_common.h>
  10 #include <amdblocks/agesawrapper.h>
  11 #include <amdblocks/agesawrapper_call.h>
  12 #include <amdblocks/amd_pci_mmconf.h>
  13 #include <amdblocks/biosram.h>
  14 #include <amdblocks/iomap.h>
  15 #include <amdblocks/post_codes.h>
  16 #include <soc/pci_devs.h>
  17 #include <soc/cpu.h>
  18 #include <soc/southbridge.h>
  19 #include <timestamp.h>
  20 #include <halt.h>
  21
  22 #if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000
  23 #error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB"
  24 #endif
  25 #if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000
  26 #error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB"
  27 #endif
  28
  29 /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */
  30 static void amd_initmmio(void)
  31 {
  32         msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
  33         int mtrr;
  34
  35         /*
  36          * todo: AGESA currently writes variable MTRRs.  Once that is
  37          *       corrected, un-hardcode this MTRR.
  38          *
  39          *       Be careful not to use get_free_var_mtrr/set_var_mtrr pairs
  40          *       where all cores execute the path.  Both cores within a compute
  41          *       unit share MTRRs.  Programming core0 has the appearance of
  42          *       modifying core1 too.  Using the pair again will create
  43          *       duplicate copies.
  44          */
  45         mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH;
  46         set_var_mtrr(mtrr, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
  47                      FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
  48
  49         mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP;
  50         set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE,
  51                         CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK);
  52
  53         mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM;
  54         set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE,
  55                         CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE);
  56 }
  57
  58 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
  59 {
  60         enable_pci_mmconf();
  61         amd_initmmio();
  62         /*
  63          * Call lib/bootblock.c main with BSP, shortcut for APs
  64          */
  65         if (!boot_cpu()) {
  66                 void (*ap_romstage_entry)(void) =
  67                                 (void (*)(void))get_ap_entry_ptr();
  68
  69                 ap_romstage_entry(); /* execution does not return */
  70                 halt();
  71         }
  72
  73         /* TSC cannot be relied upon. Override the TSC value passed in. */
  74         bootblock_main_with_basetime(timestamp_get());
  75 }
  76
  77 void bootblock_soc_early_init(void)
  78 {
  79         bootblock_fch_early_init();
  80         post_code(POSTCODE_BOOTBLOCK_SOC_EARLY_INIT);
  81 }
  82
  83 void bootblock_soc_init(void)
  84 {
  85         if (CONFIG(AMD_SOC_CONSOLE_UART))
  86                 assert(CONFIG_UART_FOR_CONSOLE >= 0
  87                                         && CONFIG_UART_FOR_CONSOLE <= 1);
  88
  89         u32 val = cpuid_eax(1);
  90         printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
  91
  92         bootblock_fch_init();
  93 }