src/soc/intel/jasperlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <commonlib/console/post_codes.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/mmio.h>
   8 #include <device/pci.h>
   9 #include <intelblocks/lpc_lib.h>
  10 #include <intelblocks/pcr.h>
  11 #include <intelblocks/pmclib.h>
  12 #include <intelblocks/systemagent.h>
  13 #include <intelblocks/tco.h>
  14 #include <soc/p2sb.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/pcr_ids.h>
  17 #include <soc/pm.h>
  18 #include <soc/smbus.h>
  19 #include <soc/soc_chip.h>
  20 #include <soc/systemagent.h>
  21 #include <spi-generic.h>
  22 #include <static.h>
  23
  24 #define CAMERA1_CLK             0x8000 /* Camera 1 Clock */
  25 #define CAMERA2_CLK             0x8080 /* Camera 2 Clock */
  26 #define CAM_CLK_EN              (1 << 1)
  27 #define MIPI_CLK                (1 << 0)
  28 #define HDPLL_CLK               (0 << 0)
  29
  30 static void pch_enable_isclk(void)
  31 {
  32         pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
  33         pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
  34 }
  35
  36 static void pch_handle_sideband(config_t *config)
  37 {
  38         if (config->pch_isclk)
  39                 pch_enable_isclk();
  40 }
  41
  42 static void pch_finalize(void)
  43 {
  44         uint32_t reg32;
  45         uint8_t *pmcbase;
  46         config_t *config = config_of_soc();
  47
  48         /* TCO Lock down */
  49         tco_lockdown();
  50
  51         /* TODO: Add Thermal Configuration */
  52
  53         pmcbase = pmc_mmio_regs();
  54         if (config->s0ix_enable) {
  55                 /*
  56                  * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated
  57                  * before entering s0ix.
  58                  */
  59                 reg32 = read32(pmcbase + CPPMVRIC3);
  60                 reg32 &= ~USBSUSPGQDIS;
  61                 write32(pmcbase + CPPMVRIC3, reg32);
  62
  63                 if (config->cnvi_reduce_s0ix_pwr_usage) {
  64                         setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS);
  65                         setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0));
  66                 }
  67         }
  68
  69         pch_handle_sideband(config);
  70
  71         pmc_clear_pmcon_sts();
  72 }
  73
  74 static void soc_finalize(void *unused)
  75 {
  76         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  77
  78         pch_finalize();
  79         apm_control(APM_CNT_FINALIZE);
  80
  81         /* Indicate finalize step with post code */
  82         post_code(POSTCODE_OS_BOOT);
  83 }
  84
  85 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
  86 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);