src/soc/intel/meteorlake/acpi/southbridge.asl

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <intelblocks/itss.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6
   7 /* SoC PCR access */
   8 #include <soc/intel/common/acpi/pch_pcr.asl>
   9 /* IOE PCR access */
  10 #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
  11 #include <soc/intel/common/acpi/ioe_pcr.asl>
  12 #endif
  13
  14 /* PCIE src clock control */
  15 #include <soc/intel/common/acpi/pcie_clk.asl>
  16
  17 /* PCH clock */
  18 #include "camera_clock_ctl.asl"
  19
  20 /* GPIO controller */
  21 #include "gpio.asl"
  22
  23 /* ESPI 0:1f.0 */
  24 #include <soc/intel/common/block/acpi/acpi/lpc.asl>
  25
  26 /* HDA */
  27 #include "hda.asl"
  28
  29 /* PCIE Ports */
  30 #include "pcie.asl"
  31
  32 /* Serial IO */
  33 #include "serialio.asl"
  34
  35 /* SMBus 0:1f.4 */
  36 #include <soc/intel/common/block/acpi/acpi/smbus.asl>
  37
  38 /* ISH 0:12.0 */
  39 #if CONFIG(DRIVERS_INTEL_ISH)
  40 #include <soc/intel/common/block/acpi/acpi/ish.asl>
  41 #endif
  42
  43 /* USB XHCI 0:14.0 */
  44 #include "xhci.asl"
  45
  46 /* PCI _OSC */
  47 #include <soc/intel/common/acpi/pci_osc.asl>
  48
  49 /* GbE 0:1f.6 */
  50 #if CONFIG(MAINBOARD_USES_IFD_GBE_REGION)
  51 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
  52 #endif