src/soc/intel/meteorlake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 #define __SIMPLE_DEVICE__
   9
  10 #include <acpi/acpi_pm.h>
  11 #include <console/console.h>
  12 #include <device/mmio.h>
  13 #include <device/device.h>
  14 #include <device/pci.h>
  15 #include <gpio.h>
  16 #include <intelblocks/pmclib.h>
  17 #include <intelblocks/rtc.h>
  18 #include <intelblocks/tco.h>
  19 #include <intelpch/espi.h>
  20 #include <security/vboot/vbnv.h>
  21 #include <soc/gpe.h>
  22 #include <soc/iomap.h>
  23 #include <soc/pci_devs.h>
  24 #include <soc/pm.h>
  25 #include <soc/smbus.h>
  26 #include <soc/soc_chip.h>
  27 #include <static.h>
  28 #include <types.h>
  29
  30 /*
  31  * SMI
  32  */
  33 const char *const *soc_smi_sts_array(size_t *a)
  34 {
  35         static const char *const smi_sts_bits[] = {
  36                 [BIOS_STS_BIT] = "BIOS",
  37                 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
  38                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  39                 [APM_STS_BIT] = "APM",
  40                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  41                 [PM1_STS_BIT] = "PM1",
  42                 [GPE0_STS_BIT] = "GPE0",
  43                 [GPIO_STS_BIT] = "GPI",
  44                 [MCSMI_STS_BIT] = "MCSMI",
  45                 [DEVMON_STS_BIT] = "DEVMON",
  46                 [TCO_STS_BIT] = "TCO",
  47                 [PERIODIC_STS_BIT] = "PERIODIC",
  48                 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
  49                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  50                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  51                 [MONITOR_STS_BIT] = "MONITOR",
  52                 [SPI_SMI_STS_BIT] = "SPI",
  53                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
  54                 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
  55         };
  56
  57         *a = ARRAY_SIZE(smi_sts_bits);
  58         return smi_sts_bits;
  59 }
  60
  61 /*
  62  * TCO
  63  */
  64 const char *const *soc_tco_sts_array(size_t *a)
  65 {
  66         static const char *const tco_sts_bits[] = {
  67                 [0] = "NMI2SMI",
  68                 [1] = "SW_TCO",
  69                 [2] = "TCO_INT",
  70                 [3] = "TIMEOUT",
  71                 [7] = "NEWCENTURY",
  72                 [8] = "BIOSWR",
  73                 [9] = "DMISCI",
  74                 [10] = "DMISMI",
  75                 [12] = "DMISERR",
  76                 [13] = "SLVSEL",
  77                 [16] = "INTRD_DET",
  78                 [17] = "SECOND_TO",
  79                 [18] = "BOOT",
  80                 [20] = "SMLINK_SLV"
  81         };
  82
  83         *a = ARRAY_SIZE(tco_sts_bits);
  84         return tco_sts_bits;
  85 }
  86
  87 /*
  88  * GPE0
  89  */
  90 const char *const *soc_std_gpe_sts_array(size_t *a)
  91 {
  92         static const char *const gpe_sts_bits[] = {
  93                 [1] = "HOTPLUG",
  94                 [2] = "SWGPE",
  95                 [6] = "TCO_SCI",
  96                 [7] = "SMB_WAK",
  97                 [9] = "PCI_EXP",
  98                 [10] = "BATLOW",
  99                 [11] = "PME",
 100                 [12] = "ME",
 101                 [13] = "PME_B0",
 102                 [14] = "eSPI",
 103                 [15] = "GPIO Tier-2",
 104                 [16] = "LAN_WAKE",
 105                 [18] = "WADT"
 106         };
 107
 108         *a = ARRAY_SIZE(gpe_sts_bits);
 109         return gpe_sts_bits;
 110 }
 111
 112 void pmc_set_disb(void)
 113 {
 114         /* Set the DISB after DRAM init */
 115         uint8_t disb_val;
 116         /* Only care about bits [23:16] of register GEN_PMCON_A */
 117         uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
 118
 119         disb_val = read8(addr);
 120         disb_val |= (DISB >> 16);
 121
 122         /* Don't clear bits that are write-1-to-clear */
 123         disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
 124         write8(addr, disb_val);
 125 }
 126
 127 /*
 128  * PMC controller gets hidden from PCI bus
 129  * during FSP-Silicon init call. Hence PWRMBASE
 130  * can't be accessible using PCI configuration space
 131  * read/write.
 132  */
 133 uint8_t *pmc_mmio_regs(void)
 134 {
 135         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 136 }
 137
 138 uint8_t *ioe_pmc_mmio_regs(void)
 139 {
 140         return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS;
 141 }
 142
 143 uintptr_t soc_read_pmc_base(void)
 144 {
 145         return (uintptr_t)pmc_mmio_regs();
 146 }
 147
 148 uint32_t *soc_pmc_etr_addr(void)
 149 {
 150         return (uint32_t *)(soc_read_pmc_base() + ETR);
 151 }
 152
 153 static void pmc_gpe0_different_values(const struct soc_intel_meteorlake_config *config)
 154 {
 155         bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
 156                          (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
 157                          (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
 158
 159         assert(result);
 160 }
 161
 162 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 163 {
 164         DEVTREE_CONST struct soc_intel_meteorlake_config *config;
 165
 166         config = config_of_soc();
 167
 168         pmc_gpe0_different_values(config);
 169
 170         /* Assign to out variable */
 171         *dw0 = config->pmc_gpe0_dw0;
 172         *dw1 = config->pmc_gpe0_dw1;
 173         *dw2 = config->pmc_gpe0_dw2;
 174 }
 175
 176 static int rtc_failed(uint32_t gen_pmcon_b)
 177 {
 178         return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
 179 }
 180
 181 int soc_get_rtc_failed(void)
 182 {
 183         const struct chipset_power_state *ps;
 184
 185         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 186                 return 1;
 187
 188         return rtc_failed(ps->gen_pmcon_b);
 189 }
 190
 191 int vbnv_cmos_failed(void)
 192 {
 193         return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 194 }
 195
 196 static inline int deep_s3_enabled(void)
 197 {
 198         uint32_t deep_s3_pol;
 199
 200         deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
 201         return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 202 }
 203
 204 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 205 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 206 {
 207         /*
 208          * Check for any power failure to determine if this a wake from
 209          * S5 because the PCH does not set the WAK_STS bit when waking
 210          * from a true G3 state.
 211          */
 212         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
 213                 prev_sleep_state = ACPI_S5;
 214
 215         /*
 216          * If waking from S3 determine if deep S3 is enabled. If not,
 217          * need to check both deep sleep well and normal suspend well.
 218          * Otherwise just check deep sleep well.
 219          */
 220         if (prev_sleep_state == ACPI_S3) {
 221                 /* PWR_FLR represents deep sleep power well loss. */
 222                 uint32_t mask = PWR_FLR;
 223
 224                 /* If deep s3 isn't enabled check the suspend well too. */
 225                 if (!deep_s3_enabled())
 226                         mask |= SUS_PWR_FLR;
 227
 228                 if (ps->gen_pmcon_a & mask)
 229                         prev_sleep_state = ACPI_S5;
 230         }
 231
 232         return prev_sleep_state;
 233 }
 234
 235 void soc_fill_power_state(struct chipset_power_state *ps)
 236 {
 237         uint8_t *pmc;
 238
 239         ps->tco1_sts = tco_read_reg(TCO1_STS);
 240         ps->tco2_sts = tco_read_reg(TCO2_STS);
 241
 242         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
 243
 244         pmc = pmc_mmio_regs();
 245         ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
 246         ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 247         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 248         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 249         ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
 250
 251         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 252                 ps->gen_pmcon_a, ps->gen_pmcon_b);
 253
 254         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 255                 ps->gblrst_cause[0], ps->gblrst_cause[1]);
 256
 257         printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
 258 }
 259
 260 /* STM Support */
 261 uint16_t get_pmbase(void)
 262 {
 263         return (uint16_t)ACPI_BASE_ADDRESS;
 264 }
 265
 266 /*
 267  * Set which power state system will be after reapplying
 268  * the power (from G3 State)
 269  */
 270 void pmc_soc_set_afterg3_en(const bool on)
 271 {
 272         uint8_t reg8;
 273         uint8_t *const pmcbase = pmc_mmio_regs();
 274
 275         reg8 = read8(pmcbase + GEN_PMCON_A);
 276         if (on)
 277                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 278         else
 279                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 280         write8(pmcbase + GEN_PMCON_A, reg8);
 281 }