src/southbridge/intel/i82801gx/fadt.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pci_ops.h>
   4 #include <acpi/acpi.h>
   5 #include <southbridge/intel/common/pmbase.h>
   6 #include "i82801gx.h"
   7 #include "chip.h"
   8
   9 void acpi_fill_fadt(acpi_fadt_t *fadt)
  10 {
  11         struct device *dev = pcidev_on_root(0x1f, 0);
  12         struct southbridge_intel_i82801gx_config *chip = dev->chip_info;
  13         u16 pmbase = lpc_get_pmbase();
  14
  15
  16         fadt->pm1a_evt_blk = pmbase;
  17         fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
  18         fadt->pm2_cnt_blk = pmbase + PM2_CNT;
  19         fadt->pm_tmr_blk = pmbase + PM1_TMR;
  20         fadt->gpe0_blk = pmbase + GPE0_STS;
  21
  22         fadt->pm1_evt_len = 4;
  23         fadt->pm1_cnt_len = 2; /* Upper word is reserved and
  24                                   Linux complains about 32 bit. */
  25         fadt->pm2_cnt_len = 1;
  26         fadt->pm_tmr_len = 4;
  27         fadt->gpe0_blk_len = 8;
  28         fadt->p_lvl2_lat = 1;
  29         fadt->p_lvl3_lat = chip->c3_latency;
  30         fadt->duty_offset = 1;
  31         if (chip->p_cnt_throttling_supported)
  32                 fadt->duty_width = 3;
  33         else
  34                 fadt->duty_width = 0;
  35
  36         fill_fadt_extended_pm_io(fadt);
  37
  38         fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES;
  39         fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
  40                        | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
  41                        | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_C2_MP_SUPPORTED);
  42
  43         if (chip->docking_supported)
  44                 fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
  45 }