src/southbridge/intel/i82870/pcibridge.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <device/pci_ids.h>
   6 #include <device/pci_ops.h>
   7 #include "82870.h"
   8
   9 static void p64h2_pcix_init(struct device *dev)
  10 {
  11         u32 dword;
  12         u8 byte;
  13
  14         /* The purpose of changes to HCCR, ACNF, and MTT is to speed
  15          * up the PCI bus for cards having high speed transfers.
  16          */
  17         dword = 0xc2040002;
  18         pci_write_config32(dev, HCCR, dword);
  19         dword = 0x0000c3bf;
  20         pci_write_config32(dev, ACNF, dword);
  21         byte = 0x08;
  22         pci_write_config8(dev, MTT, byte);
  23 }
  24 static struct device_operations pcix_ops  = {
  25         .read_resources   = pci_bus_read_resources,
  26         .set_resources    = pci_dev_set_resources,
  27         .enable_resources = pci_bus_enable_resources,
  28         .init             = p64h2_pcix_init,
  29         .scan_bus         = pci_scan_bridge,
  30         .reset_bus        = pci_bus_reset,
  31 };
  32
  33 static const struct pci_driver pcix_driver __pci_driver = {
  34         .ops    = &pcix_ops,
  35         .vendor = PCI_VID_INTEL,
  36         .device = PCI_DID_INTEL_82870_1F0,
  37 };
  38
  39 struct chip_operations southbridge_intel_i82870_ops = {
  40         .name = "Intel 82870",
  41 };