src/vendorcode/mediatek/mt8195/include/dramc_register.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 #ifndef _A60868_REGISTER_H_
   4 #define _A60868_REGISTER_H_
   5
   6 #include "dramc_pi_api.h"
   7
   8
   9 #define POS_BANK_NUM 16  // SW Virtual base address position
  10
  11 #if (fcFOR_CHIP_ID == fc8195)
  12 #include "8195_Register_DDRPHY_MD32.h"
  13 #include "8195_Register_DDRPHY_NAO.h"
  14 #include "8195_Register_DDRPHY_AO.h"
  15 #include "8195_Register_DRAMC_AO.h"
  16 #include "8195_Register_DRAMC_NAO.h"
  17 #else
  18 #include "Register_DDRPHY_MD32.h"
  19 #include "Register_DDRPHY_NAO.h"
  20 #include "Register_DDRPHY_AO.h"
  21 #include "Register_DRAMC_AO.h"
  22 #include "Register_DRAMC_NAO.h"
  23 #include "Register_SYSTEM.h"
  24 #endif
  25
  26 #if FOR_DV_SIMULATION_USED
  27 #define Channel_A_DRAMC_NAO_BASE_VIRTUAL        0x40000
  28 #define Channel_B_DRAMC_NAO_BASE_VIRTUAL        0x50000
  29 #define Channel_A_DRAMC_AO_BASE_VIRTUAL         0x60000
  30 #define Channel_B_DRAMC_AO_BASE_VIRTUAL         0x70000
  31 #define Channel_A_DDRPHY_NAO_BASE_VIRTUAL       0x80000
  32 #define Channel_B_DDRPHY_NAO_BASE_VIRTUAL       0x90000
  33 #define Channel_A_DDRPHY_AO_BASE_VIRTUAL        0xA0000
  34 #define Channel_B_DDRPHY_AO_BASE_VIRTUAL        0xB0000
  35 #define Channel_A_DDRPHY_DPM_BASE_VIRTUAL       0xC0000
  36 #define MAX_BASE_VIRTUAL                        0xD0000
  37 #else
  38 // SW Virtual base address
  39 #define Channel_A_DRAMC_NAO_BASE_VIRTUAL        0x40000
  40 #define Channel_B_DRAMC_NAO_BASE_VIRTUAL        0x50000
  41 #define Channel_C_DRAMC_NAO_BASE_VIRTUAL        0x60000
  42 #define Channel_D_DRAMC_NAO_BASE_VIRTUAL        0x70000
  43 #define Channel_A_DRAMC_AO_BASE_VIRTUAL         0x80000
  44 #define Channel_B_DRAMC_AO_BASE_VIRTUAL         0x90000
  45 #define Channel_C_DRAMC_AO_BASE_VIRTUAL         0xA0000
  46 #define Channel_D_DRAMC_AO_BASE_VIRTUAL         0xB0000
  47 #define Channel_A_DDRPHY_NAO_BASE_VIRTUAL       0xC0000
  48 #define Channel_B_DDRPHY_NAO_BASE_VIRTUAL       0xD0000
  49 #define Channel_C_DDRPHY_NAO_BASE_VIRTUAL       0xE0000
  50 #define Channel_D_DDRPHY_NAO_BASE_VIRTUAL       0xF0000
  51 #define Channel_A_DDRPHY_AO_BASE_VIRTUAL        0x100000
  52 #define Channel_B_DDRPHY_AO_BASE_VIRTUAL        0x110000
  53 #define Channel_C_DDRPHY_AO_BASE_VIRTUAL        0x120000
  54 #define Channel_D_DDRPHY_AO_BASE_VIRTUAL        0x130000
  55 #define Channel_A_DDRPHY_DPM_BASE_VIRTUAL       0x140000
  56 #define Channel_B_DDRPHY_DPM_BASE_VIRTUAL       0x150000
  57 #define MAX_BASE_VIRTUAL                        0x160000
  58 #endif
  59
  60 #define DRAMC_WBR 0x100010B4
  61 //#if (CHANNEL_NUM==4)
  62 #define DRAMC_BROADCAST_ON_4CH 0x27f7f  //4CH
  63 //#else
  64 #define DRAMC_BROADCAST_ON_2CH 0x7f  //2CH
  65 //#endif
  66 #define DRAMC_BROADCAST_ON 0x1
  67 #define DRAMC_BROADCAST_OFF 0x0
  68
  69 //Definitions indicating DRAMC, DDRPHY register shuffle offset
  70 #define SHU_GRP_DRAMC_OFFSET      0x700
  71 #define SHU_GRP_DDRPHY_OFFSET     0x700
  72
  73 #define DRAMC_REG_AO_SHU_OFFSET                 (0x700)
  74 #define DRAMC_REG_AO_RANK_OFFSET                (0x200)
  75 #define DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR (DRAMC_REG_RK_TEST2_A1 - DRAMC_AO_BASE_ADDRESS) // 0x0500
  76 #define DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR  (DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
  77 #define DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
  78 #define DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR  (DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
  79 #define DRAMC_REG_AO_SHUFFLE0_BASE_ADDR         (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
  80 #define DRAMC_REG_AO_SHUFFLE0_END_ADDR          (DRAMC_REG_SHU_ACTIM7 - DRAMC_AO_BASE_ADDRESS) // 0x16E8
  81
  82 #define DDRPHY_AO_B0_B1_OFFSET                  (0x180)
  83 #define DDRPHY_AO_SHU_OFFSET                    (0x700)
  84 #define DDRPHY_AO_RANK_OFFSET                   (0x80)
  85 #define DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_B0_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0060
  86 #define DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  87 #define DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_B1_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x01E0
  88 #define DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  89 #define DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_CA_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0360
  90 #define DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  91 #define DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_B0_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0760
  92 #define DDRPHY_AO_RANK0_B0_SHU0_END_ADDR        (DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  93 #define DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_B1_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x08E0
  94 #define DDRPHY_AO_RANK0_B1_SHU0_END_ADDR        (DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  95 #define DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_CA_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0A60
  96 #define DDRPHY_AO_RANK0_CA_SHU0_END_ADDR        (DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  97 #define DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR     (DDRPHY_REG_MISC_SHU_RK_DQSCTL - DDRPHY_AO_BASE_ADDRESS) // 0x0BE0
  98 #define DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR      (DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  99 #define DDRPHY_AO_SHUFFLE0_BASE_ADDR            (DDRPHY_REG_SHU_PHYPLL0 - DDRPHY_AO_BASE_ADDRESS) // 0x700
 100 #define DDRPHY_AO_SHUFFLE0_END_ADDR             (DDRPHY_REG_MISC_SHU_CG_CTRL0 - DDRPHY_AO_BASE_ADDRESS) // 0xDA4
 101
 102 #define DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET        (0x20)
 103 #define DDRPHY_NAO_GATING_STATUS_RK_OFFSET              (0x10)
 104 #define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0600
 105 #define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
 106 #define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0640
 107 #define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
 108 #define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0680
 109 #define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
 110 #define DDRPHY_NAO_RANK0_GATING_STATUS_START            (DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0420
 111 #define DDRPHY_NAO_RANK0_GATING_STATUS_END              (DDRPHY_NAO_RANK0_GATING_STATUS_START + DDRPHY_NAO_GATING_STATUS_RK_OFFSET)
 112
 113 #define DRAMC_REG_NAO_RANK_OFFSET                (0x200)
 114 #define DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR (DRAMC_REG_MR_BACKUP_00_RK0_FSP0 - DRAMC_NAO_BASE_ADDRESS) // 0x0900
 115 #define DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR  (DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR + DRAMC_REG_NAO_RANK_OFFSET)
 116
 117 // HW Physical base address
 118 #if defined(__DPM__)
 119 /* MD32 address */
 120 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
 121 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x300A2000
 122 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
 123 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x300B2000
 124 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 125 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
 126 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 127 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
 128 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 129 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x300A8000
 130 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 131 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x300B8000
 132 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 133 #define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x0
 134 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 135 #define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x0
 136 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 137 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x300A6000
 138 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 139 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x300B6000
 140 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 141 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
 142 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 143 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
 144 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 145 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x300AA000
 146 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 147 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x300BA000
 148 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 149 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x0
 150 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 151 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x0
 152 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 153 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x30040000
 154 #elif (FOR_DV_SIMULATION_USED)
 155 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
 156 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x10000
 157 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
 158 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x40000
 159 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 160 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
 161 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 162 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
 163
 164 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 165 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x20000
 166 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 167 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x50000
 168 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 169 #define Channel_C_DRAMC_NAO_BASE_ADDRESS         0x0
 170 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 171 #define Channel_D_DRAMC_NAO_BASE_ADDRESS         0x0
 172
 173 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 174 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x30000
 175 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 176 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x60000
 177 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 178 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
 179 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 180 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
 181
 182 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 183 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x70000
 184 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 185 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x80000
 186 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 187 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS        0x0
 188 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 189 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS        0x0
 190
 191 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 192 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0xD0000
 193 #elif(HAPS_FPFG_A60868 ==0)
 194 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
 195 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x10230000
 196 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
 197 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x10240000
 198 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 199 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x10250000
 200 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 201 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x10260000
 202 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 203 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x10234000
 204 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 205 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x10244000
 206 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 207 #define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x10254000
 208 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 209 #define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x10264000
 210 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 211 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x10238000
 212 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 213 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x10248000
 214 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 215 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x10258000
 216 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 217 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x10268000
 218 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 219 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x10236000
 220 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 221 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x10246000
 222 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 223 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x10256000
 224 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 225 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x10266000
 226 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 227 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x10940000
 228 #undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
 229 #define Channel_B_DDRPHY_DPM_BASE_ADDRESS       0x10A40000
 230 #else  // A60868 FPGA Base Address
 231 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
 232 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x40000
 233 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
 234 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x0
 235 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 236 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
 237 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 238 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
 239 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 240 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x10000
 241 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 242 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x0
 243 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 244 #define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x0
 245 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 246 #define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x0
 247 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 248 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x70000
 249 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 250 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x0
 251 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 252 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
 253 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 254 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
 255 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 256 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x80000
 257 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 258 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x0
 259 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 260 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x0
 261 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 262 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x0
 263 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 264 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x100000
 265 #undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
 266 #define Channel_B_DDRPHY_DPM_BASE_ADDRESS       0x0
 267 #endif
 268
 269 #define CHK_INCLUDE_LOCAL_HEADER "\n ==> Include local header but not one at DV SERVER\n\n"
 270
 271
 272 #endif // _A60868_REGISTER_H_