util/marvell/doimage_mv/bootstrap_os.h

   1 /*******************************************************************************
   2 Copyright (C) Marvell International Ltd. and its affiliates
   3
   4 Marvell GPL License Option
   5
   6 If you received this File from Marvell, you may opt to use, redistribute and/or
   7 modify this File in accordance with the terms and conditions of the General
   8 Public License Version 2, June 1991 (the "GPL License"), a copy of which is
   9 available along with the File in the license.txt file or by writing to the Free
  10 Software Foundation, Inc.
  11
  12 THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
  13 WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
  14 DISCLAIMED.  The GPL License provides additional details about this warranty
  15 disclaimer.
  16
  17 *******************************************************************************/
  18 #ifndef _INC_BOOTSTRAP_OS_H
  19 #define _INC_BOOTSTRAP_OS_H
  20
  21 /* BE/ LE swap for Asm */
  22 #if defined(MV_CPU_LE)
  23
  24 #define htoll(x) x
  25 #define HTOLL(sr, tr)
  26
  27 #elif defined(MV_CPU_BE)
  28
  29 #define htoll(x)                                                               \
  30         ((((x)&0x00ff) << 24) | (((x)&0xff00) << 8) | (((x) >> 8) & 0xff00) |  \
  31          (((x) >> 24) & 0x00ff))
  32
  33 #define HTOLL(sr, temp) do {    /*sr   = A  ,B  ,C  ,D    */        \
  34         eor temp, sr, sr, ROR #16; /*temp = A^C,B^D,C^A,D^B  */     \
  35         bic temp, temp, #0xFF0000; /*temp = A^C,0  ,C^A,D^B  */      \
  36         mov sr, sr, ROR #8;     /*sr   = D  ,A  ,B  ,C    */         \
  37         eor sr, sr, temp, LSR #8   /*sr   = D  ,C  ,B  ,A    */     \
  38         } while (0)
  39
  40 #endif
  41
  42 #define MV_REG_READ_ASM(toReg, tmpReg, regOffs) do {                   \
  43         ldr tmpReg, = (INTER_REGS_BASE + regOffs);                     \
  44         ldr toReg, [tmpReg];                                           \
  45         HTOLL(toReg, tmpReg)                                            \
  46         } while (0)
  47
  48 #define MV_REG_WRITE_ASM(fromReg, tmpReg, regOffs)                             \
  49         HTOLL(fromReg, tmpReg);                                                \
  50         ldr tmpReg, = (INTER_REGS_BASE + regOffs);                             \
  51         str fromReg, [tmpReg]
  52
  53 #define MV_DV_REG_READ_ASM(toReg, tmpReg, regOffs)                             \
  54         ldr tmpReg, = (CFG_DFL_MV_REGS + regOffs);                             \
  55         ldr toReg, [tmpReg];                                                   \
  56         HTOLL(toReg, tmpReg)
  57
  58 #define MV_DV_REG_WRITE_ASM(fromReg, tmpReg, regOffs)                          \
  59         HTOLL(fromReg, tmpReg);                                                \
  60         ldr tmpReg, = (CFG_DFL_MV_REGS + regOffs);                             \
  61         str fromReg, [tmpReg]
  62
  63 /* Defines */
  64
  65 /* The following is a list of Marvell status    */
  66 #define MV_ERROR (-1)
  67 #define MV_OK (0x00)              /* Operation succeeded                   */
  68 #define MV_FAIL (0x01)            /* Operation failed                      */
  69 #define MV_BAD_VALUE (0x02)       /* Illegal value (general)               */
  70 #define MV_OUT_OF_RANGE (0x03)    /* The value is out of range             */
  71 #define MV_BAD_PARAM (0x04)       /* Illegal parameter in function called  */
  72 #define MV_BAD_PTR (0x05)        /* Illegal pointer value                 */
  73 #define MV_BAD_SIZE (0x06)      /* Illegal size                          */
  74 #define MV_BAD_STATE (0x07)       /* Illegal state of state machine        */
  75 #define MV_SET_ERROR (0x08)       /* Set operation failed                  */
  76 #define MV_GET_ERROR (0x09)       /* Get operation failed                  */
  77 #define MV_CREATE_ERROR (0x0A)    /* Fail while creating an item           */
  78 #define MV_NOT_FOUND (0x0B)       /* Item not found                        */
  79 #define MV_NO_MORE (0x0C)        /* No more items found                   */
  80 #define MV_NO_SUCH (0x0D)        /* No such item                          */
  81 #define MV_TIMEOUT (0x0E)        /* Time Out                              */
  82 #define MV_NO_CHANGE (0x0F)       /* Parameter(s) is already in this value */
  83 #define MV_NOT_SUPPORTED (0x10)   /* This request is not support           */
  84 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */
  85 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized           */
  86 #define MV_NO_RESOURCE (0x13)     /* Resource not available (memory ...)   */
  87 #define MV_FULL (0x14)            /* Item is full (Queue or table etc...)  */
  88 #define MV_EMPTY (0x15)           /* Item is empty (Queue or table etc...) */
  89 #define MV_INIT_ERROR (0x16)      /* Error occurred while INIT process      */
  90 #define MV_HW_ERROR (0x17)      /* Hardware error                        */
  91 #define MV_TX_ERROR (0x18)      /* Transmit operation not succeeded      */
  92 #define MV_RX_ERROR (0x19)      /* Receive operation not succeeded       */
  93 #define MV_NOT_READY (0x1A)       /* The other side is not ready yet       */
  94 #define MV_ALREADY_EXIST (0x1B)   /* Tried to create existing item         */
  95 #define MV_OUT_OF_CPU_MEM (0x1C)  /* Cpu memory allocation failed.         */
  96 #define MV_NOT_STARTED (0x1D)     /* Not started yet         */
  97 #define MV_BUSY (0x1E)            /* Item is busy.                         */
  98 #define MV_TERMINATE (0x1F)       /* Item terminates it's work.            */
  99 #define MV_NOT_ALIGNED (0x20)     /* Wrong alignment                       */
 100 #define MV_NOT_ALLOWED (0x21)     /* Operation NOT allowed                 */
 101 #define MV_WRITE_PROTECT (0x22)   /* Write protected                       */
 102
 103 #define MV_INVALID (int)(-1)
 104
 105 #define MV_FALSE 0
 106 #define MV_TRUE (!(MV_FALSE))
 107
 108 #ifndef NULL
 109 #define NULL ((void *)0)
 110 #endif
 111
 112 #ifndef MV_ASMLANGUAGE
 113 /* typedefs */
 114
 115 typedef char MV_8;
 116 typedef unsigned char MV_U8;
 117
 118 typedef int MV_32;
 119 typedef unsigned int MV_U32;
 120
 121 typedef short MV_16;
 122 typedef unsigned short MV_U16;
 123 /*
 124 #ifdef MV_PPC64
 125 typedef long            MV_64;
 126 typedef unsigned long   MV_U64;
 127 #else
 128 typedef long long               MV_64;
 129 typedef unsigned long long      MV_U64;
 130 #endif
 131 */
 132 typedef long MV_LONG;           /* 32/64 */
 133 typedef unsigned long MV_ULONG; /* 32/64 */
 134
 135 typedef int MV_STATUS;
 136 typedef int MV_BOOL;
 137 /*typedef void    MV_VOID;*/
 138 #define MV_VOID void
 139 typedef float MV_FLOAT;
 140
 141 typedef int (*MV_FUNCPTR)(void);       /* ptr to function returning int   */
 142 typedef void (*MV_VOIDFUNCPTR)(void);  /* ptr to function returning void  */
 143 typedef double (*MV_DBLFUNCPTR)(void); /* ptr to function returning double*/
 144 typedef float (*MV_FLTFUNCPTR)(void);  /* ptr to function returning float */
 145
 146 typedef MV_U32 MV_KHZ;
 147 typedef MV_U32 MV_MHZ;
 148 typedef MV_U32 MV_HZ;
 149 #if defined(_HOST_COMPILER)
 150 #define __MV_PACKED
 151 #else
 152 #define __MV_PACKED /*__packed*/
 153 #endif
 154
 155 #endif /* MV_ASMLANGUAGE */
 156
 157 /* Bit field definitions */
 158 #define NO_BIT 0x00000000
 159 #define BIT0 0x00000001
 160 #define BIT1 0x00000002
 161 #define BIT2 0x00000004
 162 #define BIT3 0x00000008
 163 #define BIT4 0x00000010
 164 #define BIT5 0x00000020
 165 #define BIT6 0x00000040
 166 #define BIT7 0x00000080
 167 #define BIT8 0x00000100
 168 #define BIT9 0x00000200
 169 #define BIT10 0x00000400
 170 #define BIT11 0x00000800
 171 #define BIT12 0x00001000
 172 #define BIT13 0x00002000
 173 #define BIT14 0x00004000
 174 #define BIT15 0x00008000
 175 #define BIT16 0x00010000
 176 #define BIT17 0x00020000
 177 #define BIT18 0x00040000
 178 #define BIT19 0x00080000
 179 #define BIT20 0x00100000
 180 #define BIT21 0x00200000
 181 #define BIT22 0x00400000
 182 #define BIT23 0x00800000
 183 #define BIT24 0x01000000
 184 #define BIT25 0x02000000
 185 #define BIT26 0x04000000
 186 #define BIT27 0x08000000
 187 #define BIT28 0x10000000
 188 #define BIT29 0x20000000
 189 #define BIT30 0x40000000
 190 #define BIT31 0x80000000
 191
 192 /* includes */
 193 #define _1K 0x00000400
 194 #define _4K 0x00001000
 195 #define _8K 0x00002000
 196 #define _16K 0x00004000
 197 #define _32K 0x00008000
 198 #define _64K 0x00010000
 199 #define _128K 0x00020000
 200 #define _256K 0x00040000
 201 #define _512K 0x00080000
 202 /* Sizes */
 203 #define _1M 0x00100000
 204 #define _2M 0x00200000
 205 #define _4M 0x00400000
 206 #define _8M 0x00800000
 207 #define _16M 0x01000000
 208 #define _32M 0x02000000
 209 #define _64M 0x04000000
 210 #define _128M 0x08000000
 211 #define _256M 0x10000000
 212 #define _512M 0x20000000
 213 #define _1G 0x40000000
 214 #define _2G 0x80000000
 215 /* Speed */
 216 #define _25MHZ 25000000
 217 #define _125MHZ 125000000
 218 #define _133MHZ 133333333
 219 #define _150MHZ 150000000
 220 #define _166MHZ 166666667
 221 #define _200MHZ 200000000
 222 #define _250MHZ 250000000
 223
 224 /* Swap tool */
 225
 226 /* 16bit nibble swap. For example 0x1234 -> 0x2143                          */
 227 #define MV_NIBBLE_SWAP_16BIT(X)                                                \
 228         (((X & 0xf) << 4) | ((X & 0xf0) >> 4) | ((X & 0xf00) << 4) |           \
 229          ((X & 0xf000) >> 4))
 230
 231 /* 32bit nibble swap. For example 0x12345678 -> 0x21436587                  */
 232 #define MV_NIBBLE_SWAP_32BIT(X)                                                \
 233         (((X & 0xf) << 4) | ((X & 0xf0) >> 4) | ((X & 0xf00) << 4) |           \
 234          ((X & 0xf000) >> 4) | ((X & 0xf0000) << 4) | ((X & 0xf00000) >> 4) |  \
 235          ((X & 0xf000000) << 4) | ((X & 0xf0000000) >> 4))
 236
 237 /* 16bit byte swap. For example 0x1122 -> 0x2211                            */
 238 #define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff) << 8) | (((X)&0xff00) >> 8))
 239
 240 /* 32bit byte swap. For example 0x11223344 -> 0x44332211                    */
 241 #define MV_BYTE_SWAP_32BIT(X)                                                  \
 242         ((((X)&0xff) << 24) | (((X)&0xff00) << 8) | (((X)&0xff0000) >> 8) |    \
 243          (((X)&0xff000000) >> 24))
 244
 245 /* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211  */
 246 #define MV_BYTE_SWAP_64BIT(X)                                                  \
 247         ((l64)((((X)&0xffULL) << 56) | (((X)&0xff00ULL) << 40) |               \
 248                (((X)&0xff0000ULL) << 24) | (((X)&0xff000000ULL) << 8) |        \
 249                (((X)&0xff00000000ULL) >> 8) |                                  \
 250                (((X)&0xff0000000000ULL) >> 24) |                               \
 251                (((X)&0xff000000000000ULL) >> 40) |                             \
 252                (((X)&0xff00000000000000ULL) >> 56)))
 253
 254 /* Endianness macros.                                                        */
 255 #if defined(MV_CPU_LE)
 256 #define MV_16BIT_LE(X) (X)
 257 #define MV_32BIT_LE(X) (X)
 258 #define MV_64BIT_LE(X) (X)
 259 #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X)
 260 #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X)
 261 #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X)
 262 #elif defined(MV_CPU_BE)
 263 #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X)
 264 #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X)
 265 #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X)
 266 #define MV_16BIT_BE(X) (X)
 267 #define MV_32BIT_BE(X) (X)
 268 #define MV_64BIT_BE(X) (X)
 269 #else
 270 #error "CPU endianness isn't defined!\n"
 271 #endif
 272
 273 #ifndef MV_ASMLANGUAGE
 274 /* Get the min between 'a' or 'b'                                           */
 275 #define MV_MIN(a, b) (((a) < (b)) ? (a) : (b))
 276
 277 /* Marvell controller register read/write macros */
 278 #define CPU_PHY_MEM(x) ((MV_U32) x)
 279 #define CPU_MEMIO_CACHED_ADDR(x) ((void *) x)
 280 #define CPU_MEMIO_UNCACHED_ADDR(x) ((void *) x)
 281
 282 /* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */
 283 #define MV_MEMIO32_WRITE(addr, data)                                           \
 284         ((*((volatile unsigned int *)(addr))) = ((unsigned int)(data)))
 285
 286 #define MV_MEMIO32_READ(addr) ((*((volatile unsigned int *)(addr))))
 287
 288 #define MV_MEMIO16_WRITE(addr, data)                                           \
 289         ((*((volatile unsigned short *)(addr))) = ((unsigned short)(data)))
 290
 291 #define MV_MEMIO16_READ(addr) ((*((volatile unsigned short *)(addr))))
 292
 293 #define MV_MEMIO8_WRITE(addr, data)                                            \
 294         ((*((volatile unsigned char *)(addr))) = ((unsigned char)(data)))
 295
 296 #define MV_MEMIO8_READ(addr) ((*((volatile unsigned char *)(addr))))
 297
 298 /* No Fast Swap implementation (in assembler) for ARM */
 299 #define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val)
 300 #define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val)
 301 #define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val)
 302 #define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val)
 303
 304 /* 32 and 16 bit read/write in big/little endian mode */
 305
 306 /* 16bit write in little endian mode */
 307 #define MV_MEMIO_LE16_WRITE(addr, data)                                        \
 308         MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data))
 309
 310 /* 16bit read in little endian mode */
 311 static inline MV_U16 MV_MEMIO_LE16_READ(void *addr)
 312 {
 313         MV_U16 data;
 314         MV_U16 *addr1 = (MV_U16 *)addr;
 315
 316         data = (MV_U16)MV_MEMIO16_READ(addr1);
 317
 318         return (MV_U16)MV_16BIT_LE_FAST(data);
 319 }
 320
 321 /* 32bit write in little endian mode */
 322 #define MV_MEMIO_LE32_WRITE(addr, data)                                        \
 323         MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data))
 324
 325 /* 32bit read in little endian mode */
 326 static inline MV_U32 MV_MEMIO_LE32_READ(void *addr)
 327 {
 328         MV_U32 data;
 329         MV_U32 *addr1 = (MV_U32 *)addr;
 330
 331         data = (MV_U32)MV_MEMIO32_READ(addr1);
 332
 333         return (MV_U32)MV_32BIT_LE_FAST(data);
 334 }
 335
 336 /* Flash APIs */
 337 #define MV_FL_8_READ MV_MEMIO8_READ
 338 #define MV_FL_16_READ MV_MEMIO_LE16_READ
 339 #define MV_FL_32_READ MV_MEMIO_LE32_READ
 340 #define MV_FL_8_DATA_READ MV_MEMIO8_READ
 341 #define MV_FL_16_DATA_READ MV_MEMIO16_READ
 342 #define MV_FL_32_DATA_READ MV_MEMIO32_READ
 343 #define MV_FL_8_WRITE MV_MEMIO8_WRITE
 344 #define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE
 345 #define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE
 346 #define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE
 347 #define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE
 348 #define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE
 349
 350 /* CPU cache information */
 351 #define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
 352 #define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
 353
 354 #define MV_REG_VALUE(offset) (MV_MEMIO32_READ((INTER_REGS_BASE | (offset))))
 355
 356 #define MV_REG_READ(offset) (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset)))
 357
 358 #define MV_REG_WRITE(offset, val)                                              \
 359         MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val))
 360
 361 #define MV_REG_BYTE_READ(offset) (MV_MEMIO8_READ((INTER_REGS_BASE | (offset))))
 362
 363 #define MV_REG_BYTE_WRITE(offset, val)                                         \
 364         MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val))
 365
 366 #define MV_REG_SHORT_READ(offset)                                              \
 367         (MV_MEMIO_LE16_READ(INTER_REGS_BASE | (offset)))
 368
 369 #define MV_REG_BIT_SET(offset, bitMask)                                        \
 370         (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)),                        \
 371                           (MV_MEMIO32_READ((INTER_REGS_BASE | (offset))) |     \
 372                            MV_32BIT_LE_FAST((bitMask)))))
 373
 374 #define MV_REG_BIT_RESET(offset, bitMask)                                      \
 375         (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)),                        \
 376                           (MV_MEMIO32_READ((INTER_REGS_BASE | (offset))) &     \
 377                            MV_32BIT_LE_FAST(~(bitMask)))))
 378
 379 #define mvOsUDelay uDelay
 380 #define mvOsMDelay(msec) uDelay(msec * 1000)
 381 #define mvOsDelay(sec) mvOsMDelay(sec * 1000)
 382
 383 #define u32 MV_U32
 384 #define u16 MV_U16
 385 #define u8 MV_U8
 386 #define s16 short
 387 #define s32 long
 388 #define s8 char
 389
 390 #define UINT32 MV_U32
 391 #define UINT16 MV_U16
 392 #define UINT8 MV_U8
 393
 394 typedef UINT32 * PUINT32;
 395 typedef UINT16 * PUINT16;
 396 typedef UINT8 * PUINT8;
 397
 398 #define TRUE MV_TRUE
 399 #define FALSE MV_FALSE
 400
 401 #endif /* #ifndef MV_ASMLANGUAGE */
 402
 403 #endif /* _INC_BOOTSTRAP_OS_H */