src/soc/intel/denverton_ns/smihandler.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <arch/hlt.h>
   5 #include <arch/io.h>
   6 #include <device/pci_ops.h>
   7 #include <console/console.h>
   8 #include <cpu/x86/cache.h>
   9 #include <cpu/x86/smm.h>
  10 #include <cpu/intel/em64t100_save_state.h>
  11 #include <device/pci_def.h>
  12 #include <intelblocks/fast_spi.h>
  13 #include <smmstore.h>
  14 #include <spi-generic.h>
  15 #include <soc/iomap.h>
  16 #include <soc/soc_util.h>
  17 #include <soc/pm.h>
  18 #include <soc/nvs.h>
  19
  20 void southbridge_smi_set_eos(void)
  21 {
  22         enable_smi(EOS);
  23 }
  24
  25 static void busmaster_disable_on_bus(int bus)
  26 {
  27         int slot, func;
  28         unsigned int val;
  29         unsigned char hdr;
  30
  31         for (slot = 0; slot < 0x20; slot++) {
  32                 for (func = 0; func < 8; func++) {
  33                         u16 reg16;
  34
  35                         pci_devfn_t dev = PCI_DEV(bus, slot, func);
  36                         val = pci_read_config32(dev, PCI_VENDOR_ID);
  37
  38                         if (val == 0xffffffff || val == 0x00000000 ||
  39                             val == 0x0000ffff || val == 0xffff0000)
  40                                 continue;
  41
  42                         /* Disable Bus Mastering for this one device */
  43                         reg16 = pci_read_config16(dev, PCI_COMMAND);
  44                         reg16 &= ~PCI_COMMAND_MASTER;
  45                         pci_write_config16(dev, PCI_COMMAND, reg16);
  46
  47                         /* If this is a bridge, then follow it. */
  48                         hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
  49                         hdr &= 0x7f;
  50                         if (hdr == PCI_HEADER_TYPE_BRIDGE ||
  51                             hdr == PCI_HEADER_TYPE_CARDBUS) {
  52                                 unsigned int buses;
  53                                 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
  54                                 busmaster_disable_on_bus((buses >> 8) & 0xff);
  55                         }
  56                 }
  57         }
  58 }
  59
  60 static void southbridge_smi_sleep(void)
  61 {
  62         uint32_t reg32;
  63         uint8_t slp_typ;
  64         uint16_t pmbase = get_pmbase();
  65
  66         /* First, disable further SMIs */
  67         disable_smi(SLP_SMI_EN);
  68
  69         /* Figure out SLP_TYP */
  70         reg32 = inl((uint16_t)(pmbase + PM1_CNT));
  71         printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
  72         slp_typ = (reg32 >> 10) & 7;
  73
  74         /* Do any mainboard sleep handling */
  75         mainboard_smi_sleep((uint8_t)(slp_typ - 2));
  76
  77         /* Next, do the deed.
  78          */
  79
  80         switch (slp_typ) {
  81         case SLP_TYP_S0:
  82                 printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
  83                 break;
  84         case SLP_TYP_S1:
  85                 printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
  86                 break;
  87         case SLP_TYP_S3:
  88                 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
  89
  90                 /* Invalidate the cache before going to S3 */
  91                 wbinvd();
  92                 break;
  93         case SLP_TYP_S4:
  94                 printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
  95                 break;
  96         case SLP_TYP_S5:
  97                 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
  98
  99                 /* Disable all GPE */
 100                 disable_all_gpe();
 101
 102                 /* also iterates over all bridges on bus 0 */
 103                 busmaster_disable_on_bus(0);
 104                 break;
 105         default:
 106                 printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
 107                 break;
 108         }
 109
 110         /* Write back to the SLP register to cause the originally intended
 111          * event again. We need to set BIT13 (SLP_EN) though to make the
 112          * sleep happen.
 113          */
 114         enable_pm1_control(SLP_EN);
 115
 116         /* Make sure to stop executing code here for S3/S4/S5 */
 117         if (slp_typ > 1)
 118                 hlt();
 119
 120         /* In most sleep states, the code flow of this function ends at
 121          * the line above. However, if we entered sleep state S1 and wake
 122          * up again, we will continue to execute code in this function.
 123          */
 124         reg32 = inl((uint16_t)(pmbase + PM1_CNT));
 125         if (reg32 & SCI_EN) {
 126                 /* The OS is not an ACPI OS, so we set the state to S0 */
 127                 disable_pm1_control(SLP_EN | SLP_TYP);
 128         }
 129 }
 130
 131 /*
 132  * Look for Synchronous IO SMI and use save state from that
 133  * core in case we are not running on the same core that
 134  * initiated the IO transaction.
 135  */
 136 static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
 137 {
 138         em64t100_smm_state_save_area_t *state;
 139         int node;
 140
 141         /* Check all nodes looking for the one that issued the IO */
 142         for (node = 0; node < CONFIG_MAX_CPUS; node++) {
 143                 state = smm_get_save_state(node);
 144
 145                 /* Check for Synchronous IO (bit0==1) */
 146                 if (!(state->io_misc_info & (1 << 0)))
 147                         continue;
 148
 149                 /* Make sure it was a write (bit4==0) */
 150                 if (state->io_misc_info & (1 << 4))
 151                         continue;
 152
 153                 /* Check for APMC IO port */
 154                 if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
 155                         continue;
 156
 157                 /* Check AX against the requested command */
 158                 if ((state->rax & 0xff) != cmd)
 159                         continue;
 160
 161                 return state;
 162         }
 163
 164         return NULL;
 165 }
 166
 167 static void finalize(void)
 168 {
 169         static int finalize_done;
 170
 171         if (finalize_done) {
 172                 printk(BIOS_DEBUG, "SMM already finalized.\n");
 173                 return;
 174         }
 175         finalize_done = 1;
 176
 177         if (CONFIG(SPI_FLASH_SMM))
 178                 /* Re-init SPI driver to handle locked BAR */
 179                 fast_spi_init();
 180 }
 181
 182 static void southbridge_smi_store(void)
 183 {
 184         u8 sub_command, ret;
 185         em64t100_smm_state_save_area_t *io_smi =
 186                 smi_apmc_find_state_save(APM_CNT_SMMSTORE);
 187         uint32_t reg_ebx;
 188
 189         if (!io_smi)
 190                 return;
 191         /* Command and return value in EAX */
 192         sub_command = (io_smi->rax >> 8) & 0xff;
 193
 194         /* Parameter buffer in EBX */
 195         reg_ebx = io_smi->rbx;
 196
 197         /* drivers/smmstore/smi.c */
 198         ret = smmstore_exec(sub_command, (void *)reg_ebx);
 199         io_smi->rax = ret;
 200 }
 201
 202 static void southbridge_smi_apmc(void)
 203 {
 204         uint8_t reg8;
 205
 206         reg8 = apm_get_apmc();
 207         switch (reg8) {
 208         case APM_CNT_ACPI_DISABLE:
 209                 disable_pm1_control(SCI_EN);
 210                 break;
 211         case APM_CNT_ACPI_ENABLE:
 212                 enable_pm1_control(SCI_EN);
 213                 break;
 214         case APM_CNT_FINALIZE:
 215                 finalize();
 216                 break;
 217         case APM_CNT_SMMSTORE:
 218                 if (CONFIG(SMMSTORE))
 219                         southbridge_smi_store();
 220                 break;
 221         }
 222
 223         mainboard_smi_apmc(reg8);
 224 }
 225
 226 static void southbridge_smi_pm1(void)
 227 {
 228         uint16_t pm1_sts = clear_pm1_status();
 229
 230         /* While OSPM is not active, poweroff immediately
 231          * on a power button event.
 232          */
 233         if (pm1_sts & PWRBTN_STS) {
 234                 // power button pressed
 235                 disable_pm1_control(-1UL);
 236                 enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
 237         }
 238 }
 239
 240 static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
 241
 242 static void southbridge_smi_tco(void)
 243 {
 244         uint32_t tco_sts = clear_tco_status();
 245
 246         /* Any TCO event? */
 247         if (!tco_sts)
 248                 return;
 249
 250         if (tco_sts & TCO1_STS_TIMEOUT) { /* TIMEOUT */
 251                 /* Handle TCO timeout */
 252                 printk(BIOS_DEBUG, "TCO Timeout.\n");
 253         }
 254 }
 255
 256 static void southbridge_smi_periodic(void)
 257 {
 258         uint32_t reg32;
 259
 260         reg32 = inl((uint16_t)(get_pmbase() + SMI_EN));
 261
 262         /* Are periodic SMIs enabled? */
 263         if ((reg32 & PERIODIC_EN) == 0)
 264                 return;
 265
 266         printk(BIOS_DEBUG, "Periodic SMI.\n");
 267 }
 268
 269 typedef void (*smi_handler_t)(void);
 270
 271 static const smi_handler_t southbridge_smi[32] = {
 272         NULL,                     //  [0] reserved
 273         NULL,                     //  [1] reserved
 274         NULL,                     //  [2] BIOS_STS
 275         NULL,                     //  [3] LEGACY_USB_STS
 276         southbridge_smi_sleep,    //  [4] SLP_SMI_STS
 277         southbridge_smi_apmc,     //  [5] APM_STS
 278         NULL,                     //  [6] SWSMI_TMR_STS
 279         NULL,                     //  [7] reserved
 280         southbridge_smi_pm1,      //  [8] PM1_STS
 281         southbridge_smi_gpe0,     //  [9] GPE0_STS
 282         NULL,                     // [10] reserved
 283         NULL,                     // [11] reserved
 284         NULL,                     // [12] reserved
 285         southbridge_smi_tco,      // [13] TCO_STS
 286         southbridge_smi_periodic, // [14] PERIODIC_STS
 287         NULL,                     // [15] SERIRQ_SMI_STS
 288         NULL,                     // [16] SMBUS_SMI_STS
 289         NULL,                     // [17] LEGACY_USB2_STS
 290         NULL,                     // [18] INTEL_USB2_STS
 291         NULL,                     // [19] reserved
 292         NULL,                     // [20] PCI_EXP_SMI_STS
 293         NULL,                     // [21] reserved
 294         NULL,                     // [22] reserved
 295         NULL,                     // [23] reserved
 296         NULL,                     // [24] reserved
 297         NULL,                     // [25] reserved
 298         NULL,                     // [26] SPI_STS
 299         NULL,                     // [27] reserved
 300         NULL,                     // [28] PUNIT
 301         NULL,                     // [29] GUNIT
 302         NULL,                     // [30] reserved
 303         NULL                      // [31] reserved
 304 };
 305
 306 void southbridge_smi_handler(void)
 307 {
 308         int i;
 309         uint32_t smi_sts;
 310
 311         /* We need to clear the SMI status registers, or we won't see what's
 312          * happening in the following calls.
 313          */
 314         smi_sts = clear_smi_status();
 315
 316         /* Call SMI sub handler for each of the status bits */
 317         for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
 318                 if (!(smi_sts & (1 << i)))
 319                         continue;
 320
 321                 if (southbridge_smi[i] != NULL) {
 322                         southbridge_smi[i]();
 323                 } else {
 324                         printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
 325                                            "handler available.\n",
 326                                i);
 327                 }
 328         }
 329 }