src/soc/intel/tigerlake/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2 ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
   3
   4 subdirs-y += romstage
   5 subdirs-y += ../../../cpu/intel/microcode
   6 subdirs-y += ../../../cpu/intel/turbo
   7
   8 # all (bootblock, verstage, romstage, postcar, ramstage)
   9 all-y += gspi.c
  10 all-y += i2c.c
  11 all-y += pmutil.c
  12 all-y += spi.c
  13 all-y += uart.c
  14
  15 bootblock-y += bootblock/bootblock.c
  16 bootblock-y += bootblock/pch.c
  17 bootblock-y += bootblock/report_platform.c
  18 bootblock-y += espi.c
  19 bootblock-y += p2sb.c
  20
  21 romstage-y += espi.c
  22 romstage-y += meminit.c
  23 romstage-y += pcie_rp.c
  24 romstage-y += reset.c
  25
  26 ramstage-y += acpi.c
  27 ramstage-y += chip.c
  28 ramstage-y += cpu.c
  29 ramstage-y += elog.c
  30 ramstage-y += espi.c
  31 ramstage-y += finalize.c
  32 ramstage-y += fsp_params.c
  33 ramstage-y += graphics.c
  34 ramstage-y += lockdown.c
  35 ramstage-y += lpm.c
  36 ramstage-y += p2sb.c
  37 ramstage-y += pcie_rp.c
  38 ramstage-y += pmc.c
  39 ramstage-y += reset.c
  40 ramstage-y += retimer.c
  41 ramstage-y += soundwire.c
  42 ramstage-y += systemagent.c
  43 ramstage-y += tcss.c
  44 ramstage-y += xhci.c
  45 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
  46
  47 smm-y += p2sb.c
  48 smm-y += pmutil.c
  49 smm-y += smihandler.c
  50 smm-y += uart.c
  51 smm-y += elog.c
  52 smm-y += xhci.c
  53
  54 ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_PCH_H),y)
  55 bootblock-y += gpio_pch_h.c
  56 romstage-y += gpio_pch_h.c
  57 ramstage-y += gpio_pch_h.c
  58 smm-y += gpio_pch_h.c
  59 verstage-y += gpio_pch_h.c
  60 else
  61 bootblock-y += gpio.c
  62 romstage-y += gpio.c
  63 ramstage-y += gpio.c
  64 smm-y += gpio.c
  65 verstage-y += gpio.c
  66 endif
  67
  68 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
  69 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
  70
  71 ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_PCH_H),y)
  72 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8d-01
  73 else
  74 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-01
  75 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-02
  76 endif
  77
  78 endif