1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* Driver for Genesys Logic GL9763E */
5 #include <console/console.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pci_ops.h>
9 #include <device/pci_ids.h>
12 static void gl9763e_init(struct device
*dev
)
16 printk(BIOS_INFO
, "GL9763E: init\n");
19 /* Set VHS (Vendor Header Space) to be writable */
20 pci_update_config32(dev
, VHS
, ~VHS_REV_MASK
, VHS_REV_W
);
21 /* Set single AXI request */
22 pci_or_config32(dev
, SCR
, SCR_AXI_REQ
);
23 /* Disable L0s support */
24 pci_and_config32(dev
, CFG_REG_2
, ~CFG_REG_2_L0S
);
26 if (CONFIG(DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX
))
27 /* Set L1 entry delay to MAX */
28 pci_or_config32(dev
, CFG_REG_2
, CFG_REG_2_L1DLY_MAX
);
30 /* Set SSC to 30000 ppm */
31 pci_update_config32(dev
, PLL_CTL_2
, ~PLL_CTL_2_MAX_SSC_MASK
, MAX_SSC_30000PPM
);
33 pci_or_config32(dev
, PLL_CTL
, PLL_CTL_SSC
);
34 /* Check chip version */
35 ver
= pci_read_config32(dev
, HW_VER_2
);
36 if ((ver
& HW_VER_MASK
) == REVISION_03
) {
37 /* Set clock source for RX path */
38 pci_update_config32(dev
, SD_CLKRX_DLY
, ~CLK_SRC_MASK
, AFTER_OUTPUT_BUFF
);
41 pci_update_config32(dev
, SD_CLKRX_DLY
, ~HS400_RX_DELAY_MASK
, HS400_RX_DELAY
);
42 /* Disable Slow mode */
43 pci_and_config32(dev
, EMMC_CTL
, ~SLOW_MODE
);
44 /* Set VHS to read-only */
45 pci_update_config32(dev
, VHS
, ~VHS_REV_MASK
, VHS_REV_R
);
48 static struct device_operations gl9763e_ops
= {
49 .read_resources
= pci_dev_read_resources
,
50 .set_resources
= pci_dev_set_resources
,
51 .enable_resources
= pci_dev_enable_resources
,
52 .ops_pci
= &pci_dev_ops_pci
,
56 static const unsigned short pci_device_ids
[] = {
61 static const struct pci_driver genesyslogic_gl9763e __pci_driver
= {
63 .vendor
= PCI_VID_GLI
,
64 .devices
= pci_device_ids
,
67 struct chip_operations drivers_generic_genesyslogic_ops
= {
68 .name
= "Genesys Logic GL9763E",