src/drivers/intel/gma/opregion.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef _COMMON_GMA_H_
   4 #define _COMMON_GMA_H_
   5
   6 #include <types.h>
   7 #include <commonlib/helpers.h>
   8
   9 /* IGD PCI Configuration register */
  10 #define ASLS           0xfc            /* OpRegion Base */
  11 #define SWSCI          0xe8            /* SWSCI Register */
  12 #define SWSMISCI       0xe0            /* SWSMISCI Register */
  13 #define GSSCIE         (1 << 0)        /* SCI Event trigger */
  14 #define SMISCISEL      (1 << 15)       /* Select SMI or SCI event source */
  15
  16 /* mailbox 0: header */
  17 typedef struct {
  18         u8      signature[16];      /* Offset 0    OpRegion signature */
  19         u32     size;               /* Offset 16   OpRegion size */
  20         struct opregion_version {
  21                 u8 rsvd;
  22                 u8 revision;
  23                 u8 minor;
  24                 u8 major;
  25         } opver;                    /* Offset 20   OpRegion version structure */
  26         u8      sbios_version[32];  /* Offset 24   System BIOS build version */
  27         u8      vbios_version[16];  /* Offset 56   Video BIOS build version */
  28         u8      driver_version[16]; /* Offset 72   Graphic drvr build version */
  29         u32     mailboxes;          /* Offset 88   Mailboxes supported */
  30         u32     dmod;               /* Offset 92   Driver Model */
  31         u32     pcon;               /* Offset 96   Platform Capabilities */
  32         u16     dver[16];           /* Offset 100  GOP Version */
  33         u8      reserved[124];      /* Offset 132  Reserved */
  34 } __packed opregion_header_t;
  35
  36 #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
  37
  38 #define IGD_MBOX1       (1 << 0)
  39 #define IGD_MBOX2       (1 << 1)
  40 #define IGD_MBOX3       (1 << 2)
  41 #define IGD_MBOX4       (1 << 3)
  42 #define IGD_MBOX5       (1 << 4)
  43
  44 #define MAILBOXES_MOBILE  (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
  45                            IGD_MBOX4 | IGD_MBOX5)
  46 #define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
  47
  48 #define SBIOS_VERSION_SIZE 32
  49
  50 /* mailbox 1: public ACPI methods */
  51 typedef struct {
  52         u32     drdy;   /* Offset 0    Driver readiness */
  53         u32     csts;   /* Offset 4    Status */
  54         u32     cevt;   /* Offset 8    Current event */
  55         u8      reserved[20];   /* Offset 12   Reserved */
  56         u32     didl;   /* Offset 32   Supported display device 1 */
  57         u32     ddl2;   /* Offset 36   Supported display device 2 */
  58         u32     ddl3;   /* Offset 40   Supported display device 3 */
  59         u32     ddl4;   /* Offset 44   Supported display device 4 */
  60         u32     ddl5;   /* Offset 48   Supported display device 5 */
  61         u32     ddl6;   /* Offset 52   Supported display device 6 */
  62         u32     ddl7;   /* Offset 56   Supported display device 7 */
  63         u32     ddl8;   /* Offset 60   Supported display device 8 */
  64         u32     cpdl;   /* Offset 64   Currently present display device 1 */
  65         u32     cpl2;   /* Offset 68   Currently present display device 2 */
  66         u32     cpl3;   /* Offset 72   Currently present display device 3 */
  67         u32     cpl4;   /* Offset 76   Currently present display device 4 */
  68         u32     cpl5;   /* Offset 80   Currently present display device 5 */
  69         u32     cpl6;   /* Offset 84   Currently present display device 6 */
  70         u32     cpl7;   /* Offset 88   Currently present display device 7 */
  71         u32     cpl8;   /* Offset 92   Currently present display device 8 */
  72         u32     cadl;   /* Offset 96   Currently active display device 1 */
  73         u32     cal2;   /* Offset 100  Currently active display device 2 */
  74         u32     cal3;   /* Offset 104  Currently active display device 3 */
  75         u32     cal4;   /* Offset 108  Currently active display device 4 */
  76         u32     cal5;   /* Offset 112  Currently active display device 5 */
  77         u32     cal6;   /* Offset 116  Currently active display device 6 */
  78         u32     cal7;   /* Offset 120  Currently active display device 7 */
  79         u32     cal8;   /* Offset 124  Currently active display device 8 */
  80         u32     nadl;   /* Offset 128  Next active device 1 */
  81         u32     ndl2;   /* Offset 132  Next active device 2 */
  82         u32     ndl3;   /* Offset 136  Next active device 3 */
  83         u32     ndl4;   /* Offset 140  Next active device 4 */
  84         u32     ndl5;   /* Offset 144  Next active device 5 */
  85         u32     ndl6;   /* Offset 148  Next active device 6 */
  86         u32     ndl7;   /* Offset 152  Next active device 7 */
  87         u32     ndl8;   /* Offset 156  Next active device 8 */
  88         u32     aslp;   /* Offset 160  ASL sleep timeout */
  89         u32     tidx;   /* Offset 164  Toggle table index */
  90         u32     chpd;   /* Offset 168  Current hot plug enable indicator */
  91         u32     clid;   /* Offset 172  Current lid state indicator */
  92         u32     cdck;   /* Offset 176  Current docking state indicator */
  93         u32     sxsw;   /* Offset 180  Display Switch notification on Sx State
  94                          * resume
  95                          */
  96         u32     evts;   /* Offset 184  Events supported by ASL */
  97         u32     cnot;   /* Offset 188  Current OS Notification */
  98         u32     nrdy;   /* Offset 192  Reasons for DRDY = 0 */
  99         u32     ddl9;   /* Offset 196  Extended Supported display device 1 */
 100         u32     dd10;   /* Offset 200  Extended Supported display device 2 */
 101         u32     dd11;   /* Offset 204  Extended Supported display device 3 */
 102         u32     dd12;   /* Offset 208  Extended Supported display device 4 */
 103         u32     dd13;   /* Offset 212  Extended Supported display device 5 */
 104         u32     dd14;   /* Offset 216  Extended Supported display device 6 */
 105         u32     dd15;   /* Offset 220  Extended Supported display device 7 */
 106         u32     cpl9;   /* Offset 224  Extended Currently present device 1 */
 107         u32     cp10;   /* Offset 228  Extended Currently present device 2 */
 108         u32     cp11;   /* Offset 232  Extended Currently present device 3 */
 109         u32     cp12;   /* Offset 236  Extended Currently present device 4 */
 110         u32     cp13;   /* Offset 240  Extended Currently present device 5 */
 111         u32     cp14;   /* Offset 244  Extended Currently present device 6 */
 112         u32     cp15;   /* Offset 248  Extended Currently present device 7 */
 113         u8      reserved2[4];   /* Offset 252  Reserved 4 bytes */
 114 } __packed opregion_mailbox1_t;
 115
 116 /* mailbox 2: software sci interface */
 117 typedef struct {
 118         u32     scic;   /* Offset 0  Software SCI function number parameters */
 119         u32     parm;   /* Offset 4  Software SCI function number parameters */
 120         u32     dslp;   /* Offset 8  Driver sleep timeout */
 121         u8      reserved[244];  /* Offset 12   Reserved */
 122 } __packed opregion_mailbox2_t;
 123
 124 /* mailbox 3: power conservation */
 125 typedef struct {
 126         u32     ardy;           /* Offset 0   Driver readiness */
 127         u32     aslc;           /* Offset 4   ASLE interrupt command / status */
 128         u32     tche;           /* Offset 8   Technology enabled indicator */
 129         u32     alsi;           /* Offset 12  Current ALS illuminance reading */
 130         u32     bclp;           /* Offset 16  Backlight brightness to set */
 131         u32     pfit;           /* Offset 20  Panel fitting Request */
 132         u32     cblv;           /* Offset 24  Brightness Current State */
 133         u16     bclm[20];       /* Offset 28  Backlight Brightness Level Duty
 134                                  *            Cycle Mapping Table
 135                                  */
 136         u32     cpfm;           /* Offset 68  Panel Fitting Current Mode */
 137         u32     epfm;           /* Offset 72  Enabled Panel Fitting Modes */
 138         u8      plut[74];       /* Offset 76  Panel Look Up Table */
 139         u32     pfmb;           /* Offset 150 PWM Frequency and Minimum
 140                                  *            Brightness
 141                                  */
 142         u32     ccdv;           /* Offset 154 Color Correction Default Values */
 143         u32     pcft;           /* Offset 158 Power Conservation Features */
 144         u32     srot;           /* Offset 162 Supported Rotation angle */
 145         u32     iuer;           /* Offset 166 Intel Ultrabook Event Register */
 146         u64     fdsp;           /* Offset 170 FFS Display Physical address */
 147         u32     fdss;           /* Offset 178 FFS Display Size */
 148         u32     stat;           /* Offset 182 State Indicator */
 149         u64     rvda;           /* Offset 186 (Igd opregion offset 0x3BAh)
 150                                  *            Physical(2.0) or relative opregion
 151                                  *            (2.1+) address of Raw VBT data
 152                                  */
 153         u32     rvds;           /* Offset 194 (Igd opregion offset 0x3C2h)
 154                                  *            Size of Raw VBT data
 155                                  */
 156         u8      reserved[58];   /* Offset 198 Reserved */
 157 } __packed opregion_mailbox3_t;
 158
 159 #define IGD_BACKLIGHT_BRIGHTNESS 0xff
 160 #define IGD_INITIAL_BRIGHTNESS 0x64
 161
 162 #define IGD_FIELD_VALID (1UL << 31)
 163 #define IGD_WORD_FIELD_VALID (1 << 15)
 164 #define IGD_PFIT_STRETCH 6
 165
 166 /* mailbox 4: vbt */
 167 typedef struct {
 168         u8 gvd1[6*KiB];
 169 } __packed opregion_vbt_t;
 170
 171 /* Mailbox 5: BIOS to Driver Notification Extension */
 172 typedef struct {
 173         u32     phed;           /* Offset 7168 Panel Header */
 174         u8      bddc[256];      /* Offset 7172 Panel EDID */
 175         u8      reserved[764];  /* Offset 7428 764 bytes */
 176 } __packed opregion_mailbox5_t;
 177
 178 /* IGD OpRegion */
 179 typedef struct {
 180         opregion_header_t       header;
 181         opregion_mailbox1_t     mailbox1;
 182         opregion_mailbox2_t     mailbox2;
 183         opregion_mailbox3_t     mailbox3;
 184         opregion_vbt_t vbt;
 185         opregion_mailbox5_t     mailbox5;
 186
 187 } __packed igd_opregion_t;
 188
 189 /* Intel Video BIOS (Option ROM) */
 190 typedef struct {
 191         u16     signature;
 192         u8      size;
 193         u8      reserved[21];
 194         u16     pcir_offset;
 195         u16     vbt_offset;
 196 } __packed optionrom_header_t;
 197
 198 #define OPROM_SIGNATURE 0xaa55
 199
 200 typedef struct {
 201         u32     signature;
 202         u16     vendor;
 203         u16     device;
 204         u16     reserved1;
 205         u16     length;
 206         u8      revision;
 207         u8      classcode[3];
 208         u16     imagelength;
 209         u16     coderevision;
 210         u8      codetype;
 211         u8      indicator;
 212         u16     reserved2;
 213 } __packed optionrom_pcir_t;
 214
 215 typedef struct {
 216         u8      hdr_signature[20];
 217         u16     hdr_version;
 218         u16     hdr_size;
 219         u16     hdr_vbt_size;
 220         u8      hdr_vbt_checksum;
 221         u8      hdr_reserved;
 222         u32     hdr_vbt_datablock;
 223         u32     hdr_aim[4];
 224         u8      datahdr_signature[16];
 225         u16     datahdr_version;
 226         u16     datahdr_size;
 227         u16     datahdr_datablocksize;
 228         u8      coreblock_id;
 229         u16     coreblock_size;
 230         u16     coreblock_biossize;
 231         u8      coreblock_biostype;
 232         u8      coreblock_releasestatus;
 233         u8      coreblock_hwsupported;
 234         u8      coreblock_integratedhw;
 235         u8      coreblock_biosbuild[4];
 236         u8      coreblock_biossignon[155];
 237 } __packed optionrom_vbt_t;
 238
 239 enum cb_err intel_gma_init_igd_opregion(void);
 240
 241 /*
 242  * Returns the CBFS filename of the VBT blob.
 243  *
 244  * The default implementation returns "vbt.bin", but other implementations can
 245  * override this.
 246  */
 247 const char *mainboard_vbt_filename(void);
 248
 249 /*
 250  * locate vbt.bin file. Returns a pointer to its content.
 251  * If vbt_size is non-NULL, also return the vbt's size.
 252  */
 253 void *locate_vbt(size_t *vbt_size);
 254
 255 #endif /* _COMMON_GMA_H_ */