mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / asus / p2b / mainboard.c
blob87838b44c341f309994c92cd73c8e4e35171ca87
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pci_ops.h>
4 #include <southbridge/intel/i82371eb/i82371eb.h>
6 /**
7 * Mainboard specific enables.
9 * @param chip_info Ignored
11 static void mainboard_init(void *chip_info)
13 const pci_devfn_t px43 = PCI_DEV(0, 4, 3);
14 u32 reg;
16 * Set up an 8-byte generic I/O decode block at device 9.
17 * This will be for W83781D hardware monitor.
18 * Port 0x290 mask 0x007
20 * This should enable access to W83781D over the ISA bus.
22 reg = pci_s_read_config32(px43, DEVRESB);
23 reg |= (0x290 | (0xe7 << 16));
24 pci_s_write_config32(px43, DEVRESB, reg);
27 struct chip_operations mainboard_ops = {
28 .init = mainboard_init