src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/agesawrapper.h>
   4 #include <variant/gpio.h>
   5 #include <soc/amd/stoneyridge/chip.h>
   6 #include <soc/pci_devs.h>
   7
   8 static const PCIe_PORT_DESCRIPTOR PortList[] = {
   9         /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
  10         {
  11                 0,
  12                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
  13                 PCIE_PORT_DATA_INITIALIZER_V2(
  14                                 PortDisabled,           /* mPortPresent */
  15                                 ChannelTypeExt6db,      /* mChannelType */
  16                                 2,                      /* mDevAddress */
  17                                 1,                      /* mDevFunction */
  18                                 HotplugDisabled,        /* mHotplug */
  19                                 PcieGenMaxSupported,    /* mMaxLinkSpeed */
  20                                 PcieGenMaxSupported,    /* mMaxLinkCap */
  21                                 AspmL0sL1,              /* mAspm */
  22                                 0,                      /* mResetId */
  23                                 0)                      /* mClkPmSupport */
  24         },
  25         /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
  26         {
  27                 0,
  28                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
  29                 PCIE_PORT_DATA_INITIALIZER_V2(
  30                                 PortEnabled,            /* mPortPresent */
  31                                 ChannelTypeExt6db,      /* mChannelType */
  32                                 2,                      /* mDevAddress */
  33                                 2,                      /* mDevFunction */
  34                                 HotplugDisabled,        /* mHotplug */
  35                                 PcieGenMaxSupported,    /* mMaxLinkSpeed */
  36                                 PcieGenMaxSupported,    /* mMaxLinkCap */
  37                                 AspmL0sL1,              /* mAspm */
  38                                 PCIE_0_RST,             /* mResetId */
  39                                 0)                      /* mClkPmSupport */
  40         },
  41         /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */
  42         {
  43                 0,
  44                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
  45                 PCIE_PORT_DATA_INITIALIZER_V2(
  46                                 PortDisabled,           /* mPortPresent */
  47                                 ChannelTypeExt6db,      /* mChannelType */
  48                                 2,                      /* mDevAddress */
  49                                 3,                      /* mDevFunction */
  50                                 HotplugDisabled,        /* mHotplug */
  51                                 PcieGenMaxSupported,    /* mMaxLinkSpeed */
  52                                 PcieGenMaxSupported,    /* mMaxLinkCap */
  53                                 AspmL0sL1,              /* mAspm */
  54                                 PCIE_1_RST,             /* mResetId */
  55                                 0)                      /* mClkPmSupport */
  56         },
  57         /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */
  58         {
  59                 0,
  60                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
  61                 PCIE_PORT_DATA_INITIALIZER_V2(
  62                                 PortEnabled,            /* mPortPresent */
  63                                 ChannelTypeExt6db,      /* mChannelType */
  64                                 2,                      /* mDevAddress */
  65                                 4,                      /* mDevFunction */
  66                                 HotplugDisabled,        /* mHotplug */
  67                                 PcieGenMaxSupported,    /* mMaxLinkSpeed */
  68                                 PcieGenMaxSupported,    /* mMaxLinkCap */
  69                                 AspmL0sL1,              /* mAspm */
  70                                 PCIE_2_RST,             /* mResetId */
  71                                 0)                      /* mClkPmSupport */
  72         },
  73         /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
  74         {
  75                 DESCRIPTOR_TERMINATE_LIST,
  76                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),
  77                 PCIE_PORT_DATA_INITIALIZER_V2(
  78                                 PortDisabled,           /* mPortPresent */
  79                                 ChannelTypeExt6db,      /* mChannelType */
  80                                 2,                      /* mDevAddress */
  81                                 5,                      /* mDevFunction */
  82                                 HotplugDisabled,        /* mHotplug */
  83                                 PcieGenMaxSupported,    /* mMaxLinkSpeed */
  84                                 PcieGenMaxSupported,    /* mMaxLinkCap */
  85                                 AspmL0sL1,              /* mAspm */
  86                                 PCIE_3_RST,             /* mResetId */
  87                                 0)                      /* mClkPmSupport */
  88         },
  89 };
  90
  91 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  92         /* DDI0 - eDP */
  93         {
  94                 0,
  95                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  96                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
  97         },
  98         /* DDI1 - DP */
  99         {
 100                 0,
 101                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
 102                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
 103         },
 104         /* DDI2 - DP */
 105         {
 106                 DESCRIPTOR_TERMINATE_LIST,
 107                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
 108                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 109         },
 110 };
 111
 112 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 113         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 114         .SocketId     = 0,
 115         .PciePortList = (void *)PortList,
 116         .DdiLinkList  = (void *)DdiList
 117 };
 118
 119 /*---------------------------------------------------------------------------*/
 120 /**
 121  *  OemCustomizeInitEarly
 122  *
 123  *  Description:
 124  *    This is the stub function will call the host environment through the
 125  *    binary block interface (call-out port) to provide a user hook opportunity.
 126  *
 127  *  Parameters:
 128  *    @param[in]      **PeiServices
 129  *    @param[in]      *InitEarly
 130  *
 131  *    @retval         VOID
 132  *
 133  **/
 134 /*---------------------------------------------------------------------------*/
 135 VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 136 {
 137         InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
 138         InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow;
 139         InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
 140         InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
 141 }