src/mainboard/google/peach_pit/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/clk.h>
   4 #include <soc/dmc.h>
   5 #include <soc/gpio.h>
   6 #include <soc/setup.h>
   7
   8 const struct mem_timings mem_timings = {
   9                 .mem_manuf = MEM_MANUF_SAMSUNG,
  10                 .mem_type = DDR_MODE_DDR3,
  11                 .frequency_mhz = 800,
  12                 .direct_cmd_msr = {
  13                         0x00020018, 0x00030000, 0x00010046, 0x00000d70,
  14                         0x00000c70
  15                 },
  16                 .timing_ref = 0x000000bb,
  17                 .timing_row = 0x6836650f,
  18                 .timing_data = 0x3630580b,
  19                 .timing_power = 0x41000a26,
  20                 .phy0_dqs = 0x08080808,
  21                 .phy1_dqs = 0x08080808,
  22                 .phy0_dq = 0x08080808,
  23                 .phy1_dq = 0x08080808,
  24                 .phy0_tFS = 0x8,
  25                 .phy1_tFS = 0x8,
  26                 .phy0_pulld_dqs = 0xf,
  27                 .phy1_pulld_dqs = 0xf,
  28
  29                 .lpddr3_ctrl_phy_reset = 0x1,
  30                 .ctrl_start_point = 0x10,
  31                 .ctrl_inc = 0x10,
  32                 .ctrl_start = 0x1,
  33                 .ctrl_dll_on = 0x1,
  34                 .ctrl_ref = 0x8,
  35
  36                 .ctrl_force = 0x1a,
  37                 .ctrl_rdlat = 0x0b,
  38                 .ctrl_bstlen = 0x08,
  39
  40                 .fp_resync = 0x8,
  41                 .iv_size = 0x7,
  42                 .dfi_init_start = 1,
  43                 .aref_en = 1,
  44
  45                 .rd_fetch = 0x3,
  46
  47                 .zq_mode_dds = 0x7,
  48                 .zq_mode_term = 0x1,
  49                 .zq_mode_noterm = 1,
  50
  51                 /*
  52                 * Dynamic Clock: Always Running
  53                 * Memory Burst length: 8
  54                 * Number of chips: 1
  55                 * Memory Bus width: 32 bit
  56                 * Memory Type: DDR3
  57                 * Additional Latancy for PLL: 0 Cycle
  58                 */
  59                 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
  60                         DMC_MEMCONTROL_DPWRDN_DISABLE |
  61                         DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
  62                         DMC_MEMCONTROL_DSREF_DISABLE |
  63                         DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
  64                         DMC_MEMCONTROL_MEM_TYPE_DDR3 |
  65                         DMC_MEMCONTROL_MEM_WIDTH_32BIT |
  66                         DMC_MEMCONTROL_NUM_CHIP_1 |
  67                         DMC_MEMCONTROL_BL_8 |
  68                         DMC_MEMCONTROL_PZQ_DISABLE |
  69                         DMC_MEMCONTROL_MRR_BYTE_7_0,
  70                 /*
  71                  * For channel interleaving, the chip_base needs to be set to
  72                  * half the bus address. So for a base address of 0x2000_0000,
  73                  * the chip_base value is 0x20 without interleaving and 0x10
  74                  * with channel interleaving. See note in section 17.14.
  75                  */
  76                 .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
  77                 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
  78                         DMC_MEMCONFIGx_CHIP_COL_10 |
  79                         DMC_MEMCONFIGx_CHIP_ROW_15 |
  80                         DMC_MEMCONFIGx_CHIP_BANK_8,
  81                 .prechconfig_tp_cnt = 0xff,
  82                 .dpwrdn_cyc = 0xff,
  83                 .dsref_cyc = 0xffff,
  84                 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
  85                         DMC_CONCONTROL_TIMEOUT_LEVEL0 |
  86                         DMC_CONCONTROL_RD_FETCH_DISABLE |
  87                         DMC_CONCONTROL_AREF_EN_DISABLE |
  88                         DMC_CONCONTROL_IO_PD_CON_DISABLE,
  89                 .dmc_channels = 1,
  90                 .chips_per_channel = 1,
  91                 .chips_to_configure = 1,
  92                 .send_zq_init = 1,
  93                 .gate_leveling_enable = 1,
  94 };