src/mainboard/google/rex/chromeos-debug-fsp.fmd

   1 FLASH 32M {
   2         SI_ALL 8M {
   3                 SI_DESC 16K
   4                 SI_ME
   5         }
   6         SI_BIOS 24M {
   7                 RW_SECTION_A 7680K {
   8                         VBLOCK_A 8K
   9                         FW_MAIN_A(CBFS)
  10                         RW_FWID_A 64
  11                 }
  12                 RW_MISC 1M {
  13                         UNIFIED_MRC_CACHE(PRESERVE) 128K {
  14                                 RECOVERY_MRC_CACHE 64K
  15                                 RW_MRC_CACHE 64K
  16                         }
  17                         RW_ELOG(PRESERVE) 16K
  18                         RW_SHARED 16K {
  19                                 SHARED_DATA 8K
  20                                 VBLOCK_DEV 8K
  21                         }
  22                         # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
  23                         # It is placed in the common `chromeos.fmd` file because it is only 4K and there
  24                         # is free space in the RW_MISC region that cannot be easily reclaimed because
  25                         # the RW_SECTION_B must start on the 16M boundary.
  26                         RW_SPD_CACHE(PRESERVE) 4K
  27                         RW_VPD(PRESERVE) 8K
  28                         RW_NVRAM(PRESERVE) 24K
  29                 }
  30                 # This section starts at the 16M boundary in SPI flash.
  31                 # MTL does not support a region crossing this boundary,
  32                 # because the SPI flash is memory-mapped into two non-
  33                 # contiguous windows.
  34                 RW_SECTION_B 7680K {
  35                         VBLOCK_B 8K
  36                         FW_MAIN_B(CBFS)
  37                         RW_FWID_B 64
  38                 }
  39                 RW_LEGACY(CBFS) 1M
  40                 RW_UNUSED 3M
  41                 # Make WP_RO region align with SPI vendor
  42                 # memory protected range specification.
  43                 WP_RO 4M {
  44                         RO_VPD(PRESERVE) 16K
  45                         RO_GSCVD 8K
  46                         RO_SECTION {
  47                                 FMAP 2K
  48                                 RO_FRID 64
  49                                 GBB@4K 12K
  50                                 COREBOOT(CBFS)
  51                         }
  52                 }
  53         }
  54 }