src/mainboard/libretrend/lt1000/gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef LT1000_GPIO_H
   4 #define LT1000_GPIO_H
   5
   6 #include <soc/gpio.h>
   7
   8 #ifndef __ACPI__
   9
  10 /* Pad configuration in ramstage. */
  11 static const struct pad_config gpio_table[] = {
  12 /* RCIN# */             PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
  13 /* LAD0 */              PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
  14 /* LAD1 */              PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
  15 /* LAD2 */              PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
  16 /* LAD3 */              PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
  17 /* LFRAME# */           PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
  18 /* SERIRQ */            PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
  19 /* PIRQA# */            PAD_NC(GPP_A7, NONE),
  20 /* CLKRUN# */           PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
  21 /* CLKOUT_LPC0 */       PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
  22 /* CLKOUT_LPC1 */       PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
  23 /* PME# */              PAD_NC(GPP_A11, NONE),
  24 /* BM_BUSY# */          PAD_NC(GPP_A12, NONE),
  25 /* SUSWARN# */          PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  26 /* SUS_STAT# */         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  27 /* SUSACK# */           PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
  28 /* SD_1P8_SEL */        PAD_NC(GPP_A16, NONE),
  29 /* SD_PWR_EN# */        PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  30 /* ISH_GP0 */           PAD_CFG_GPI(GPP_A18, NONE, DEEP),
  31 /* ISH_GP1 */           PAD_CFG_GPI(GPP_A19, NONE, DEEP),
  32 /* ISH_GP2 */           PAD_CFG_GPI(GPP_A20, NONE, DEEP),
  33 /* ISH_GP3 */           PAD_NC(GPP_A21, NONE),
  34 /* ISH_GP4 */           PAD_NC(GPP_A22, NONE),
  35 /* ISH_GP5 */           PAD_NC(GPP_A23, NONE),
  36
  37 /* CORE_VID0 */         PAD_NC(GPP_B0, NONE),
  38 /* CORE_VID1 */         PAD_NC(GPP_B1, NONE),
  39 /* VRALERT# */          PAD_NC(GPP_B2, NONE),
  40 /* CPU_GP2 */           PAD_NC(GPP_B3, NONE),
  41 /* CPU_GP3 */           PAD_NC(GPP_B4, NONE),
  42 /* SRCCLKREQ0# */       PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
  43 /* SRCCLKREQ1# */       PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  44 /* SRCCLKREQ2# */       PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  45 /* SRCCLKREQ3# */       PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  46 /* SRCCLKREQ4# */       PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
  47 /* SRCCLKREQ5# */       PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
  48 /* EXT_PWR_GATE# */     PAD_NC(GPP_B11, NONE),
  49 /* SLP_S0# */           PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  50 /* PLTRST# */           PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  51 /* SPKR */              PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
  52 /* GSPI0_CS# */         PAD_NC(GPP_B15, NONE),
  53 /* GSPI0_CLK */         PAD_NC(GPP_B16, NONE),
  54 /* GSPI0_MISO */        PAD_NC(GPP_B17, NONE),
  55 /* GSPI0_MOSI */        PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
  56 /* GSPI1_CS# */         PAD_NC(GPP_B19, NONE),
  57 /* GSPI1_CLK */         PAD_NC(GPP_B20, NONE),
  58 /* GSPI1_MISO */        PAD_NC(GPP_B21, NONE),
  59 /* GSPI1_MOSI */        PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
  60 /* SM1ALERT# */         PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
  61
  62 /* SMBCLK */            PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
  63 /* SMBDATA */           PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
  64 /* SMBALERT# */         PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
  65 /* SML0CLK */           PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
  66 /* SML0DATA */          PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
  67 /* SML0ALERT# */        PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
  68 /* SML1CLK */           PAD_NC(GPP_C6, NONE), /* RESERVED */
  69 /* SML1DATA */          PAD_NC(GPP_C7, NONE), /* RESERVED */
  70 /* UART0_RXD */         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
  71 /* UART0_TXD */         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
  72 /* UART0_RTS# */        PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
  73 /* UART0_CTS# */        PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
  74 /* UART1_RXD */         PAD_NC(GPP_C12, NONE),
  75 /* UART1_TXD */         PAD_NC(GPP_C13, NONE),
  76 /* UART1_RTS# */        PAD_NC(GPP_C14, NONE),
  77 /* UART1_CTS# */        PAD_NC(GPP_C15, NONE),
  78 /* I2C0_SDA */          PAD_CFG_GPI(GPP_C16, NONE, DEEP),
  79 /* I2C0_SCL */          PAD_CFG_GPI(GPP_C17, NONE, DEEP),
  80 /* I2C1_SDA */          PAD_CFG_GPI(GPP_C18, NONE, DEEP),
  81 /* I2C1_SCL */          PAD_NC(GPP_C19, NONE),
  82 /* UART2_RXD */         PAD_NC(GPP_C20, NONE),
  83 /* UART2_TXD */         PAD_NC(GPP_C21, NONE),
  84 /* UART2_RTS# */        PAD_NC(GPP_C22, NONE),
  85 /* UART2_CTS# */        PAD_NC(GPP_C23, NONE),
  86
  87 /* SPI1_CS# */          PAD_NC(GPP_D0, NONE),
  88 /* SPI1_CLK */          PAD_NC(GPP_D1, NONE),
  89 /* SPI1_MISO */         PAD_NC(GPP_D2, NONE),
  90 /* SPI1_MOSI */         PAD_NC(GPP_D3, NONE),
  91 /* FASHTRIG */          PAD_NC(GPP_D4, NONE),
  92 /* ISH_I2C0_SDA */      PAD_NC(GPP_D5, NONE),
  93 /* ISH_I2C0_SCL */      PAD_NC(GPP_D6, NONE),
  94 /* ISH_I2C1_SDA */      PAD_NC(GPP_D7, NONE),
  95 /* ISH_I2C1_SCL */      PAD_NC(GPP_D8, NONE),
  96 /* ISH_SPI_CS# */       PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),
  97 /* ISH_SPI_CLK */       PAD_CFG_GPI(GPP_D10, NONE, DEEP),
  98 /* ISH_SPI_MISO */      PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),
  99 /* ISH_SPI_MOSI */      PAD_NC(GPP_D12, NONE),
 100 /* ISH_UART0_RXD */     PAD_NC(GPP_D13, NONE),
 101 /* ISH_UART0_TXD */     PAD_NC(GPP_D14, NONE),
 102 /* ISH_UART0_RTS# */    PAD_NC(GPP_D15, NONE),
 103 /* ISH_UART0_CTS# */    PAD_NC(GPP_D16, NONE),
 104 /* DMIC_CLK1 */         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 105 /* DMIC_DATA1 */        PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 106 /* DMIC_CLK0 */         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 107 /* DMIC_DATA0 */        PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 108 /* SPI1_IO2 */          PAD_NC(GPP_D21, NONE),
 109 /* SPI1_IO3 */          PAD_NC(GPP_D22, NONE),
 110 /* I2S_MCLK */          PAD_NC(GPP_D23, NONE),
 111
 112 /* SATAXPCI0 */         PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
 113 /* SATAXPCIE1 */        PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
 114 /* SATAXPCIE2 */        PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
 115 /* CPU_GP0 */           PAD_NC(GPP_E3, NONE),
 116 /* SATA_DEVSLP0 */      PAD_NC(GPP_E4, NONE),
 117 /* SATA_DEVSLP1 */      PAD_NC(GPP_E5, NONE),
 118 /* SATA_DEVSLP2 */      PAD_NC(GPP_E6, NONE),
 119 /* CPU_GP1 */           PAD_NC(GPP_E7, NONE),
 120 /* SATALED# */          PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 121 /* USB2_OCO# */         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 122 /* USB2_OC1# */         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 123 /* USB2_OC2# */         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 124 /* USB2_OC3# */         PAD_NC(GPP_E12, NONE),
 125 /* DDPB_HPD0 */         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 126 /* DDPC_HPD1 */         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 127 /* DDPD_HPD2 */         PAD_NC(GPP_E15, NONE),
 128 /* DDPE_HPD3 */         PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, NONE),
 129 /* EDP_HPD */           PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 130 /* DDPB_CTRLCLK */      PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 131 /* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
 132 /* DDPC_CTRLCLK */      PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 133 /* DDPC_CTRLDATA */     PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
 134 /* DDPD_CTRLCLK */      PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP),
 135 /* DDPD_CTRLDATA */     PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),
 136
 137 /* I2S2_SCLK */         PAD_NC(GPP_F0, NONE),
 138 /* I2S2_SFRM */         PAD_NC(GPP_F1, NONE),
 139 /* I2S2_TXD */          PAD_NC(GPP_F2, NONE),
 140 /* I2S2_RXD */          PAD_NC(GPP_F3, NONE),
 141 /* I2C2_SDA */          PAD_NC(GPP_F4, NONE),
 142 /* I2C2_SCL */          PAD_NC(GPP_F5, NONE),
 143 /* I2C3_SDA */          PAD_NC(GPP_F6, NONE),
 144 /* I2C3_SCL */          PAD_NC(GPP_F7, NONE),
 145 /* I2C4_SDA */          PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
 146 /* I2C4_SCL */          PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
 147 /* I2C5_SDA */          PAD_NC(GPP_F10, NONE),
 148 /* I2C5_SCL */          PAD_NC(GPP_F11, NONE),
 149 /* EMMC_CMD */          PAD_NC(GPP_F12, NONE),
 150 /* EMMC_DATA0 */        PAD_NC(GPP_F13, NONE),
 151 /* EMMC_DATA1 */        PAD_NC(GPP_F14, NONE),
 152 /* EMMC_DATA2 */        PAD_NC(GPP_F15, NONE),
 153 /* EMMC_DATA3 */        PAD_NC(GPP_F16, NONE),
 154 /* EMMC_DATA4 */        PAD_NC(GPP_F17, NONE),
 155 /* EMMC_DATA5 */        PAD_NC(GPP_F18, NONE),
 156 /* EMMC_DATA6 */        PAD_NC(GPP_F19, NONE),
 157 /* EMMC_DATA7 */        PAD_NC(GPP_F20, NONE),
 158 /* EMMC_RCLK */         PAD_NC(GPP_F21, NONE),
 159 /* EMMC_CLK */          PAD_NC(GPP_F22, NONE),
 160 /* RSVD */              PAD_NC(GPP_F23, NONE),
 161
 162 /* SD_CMD */            PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 163 /* SD_DATA0 */          PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 164 /* SD_DATA1 */          PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 165 /* SD_DATA2 */          PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 166 /* SD_DATA3 */          PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 167 /* SD_CD# */            PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
 168 /* SD_CLK */            PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 169 /* SD_WP */             PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1),
 170
 171 /* BATLOW# */           PAD_NC(GPD0, NONE),
 172 /* ACPRESENT */         PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
 173 /* LAN_WAKE# */         PAD_NC(GPD2, NONE),
 174 /* PWRBTN# */           PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
 175 /* SLP_S3# */           PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
 176 /* SLP_S4# */           PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
 177 /* SLP_A# */            PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
 178 /* RSVD */              PAD_NC(GPD7, NONE),
 179 /* SUSCLK */            PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
 180 /* SLP_WLAN# */         PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
 181 /* SLP_S5# */           PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
 182 /* LANPHYC */           PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
 183 };
 184
 185 #endif
 186
 187 #endif