1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* DefinitionBlock Statement */
11 0x00010001 /* OEM Revision */
13 { /* Start of ASL file */
14 #include <acpi/dsdt_top.asl>
16 /* Globals for the platform */
17 #include "acpi/mainboard.asl"
19 /* Describe the USB Overcurrent pins */
20 #include "acpi/usb_oc.asl"
22 /* PCI IRQ mapping for the Southbridge */
23 #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
25 /* Contains the supported sleep states for this chipset */
26 #include <southbridge/amd/common/acpi/sleepstates.asl>
28 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
29 #include "acpi/sleep.asl"
32 Scope(\_SB) { /* Start \_SB scope */
33 /* global utility methods expected within the \_SB scope */
34 #include <arch/x86/acpi/globutil.asl>
36 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
37 #include "acpi/routing.asl"
40 /* Describe the AMD Northbridge */
41 #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
43 /* Describe the AMD Fusion Controller Hub Southbridge */
44 #include <southbridge/amd/pi/hudson/acpi/fch.asl>
47 /* Describe PCI INT[A-H] for the Southbridge */
48 #include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
50 } /* End \_SB scope */
52 /* Describe SMBUS for the Southbridge */
53 #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
55 /* Define the General Purpose Events for the platform */
56 #include "acpi/gpe.asl"