mb/google/brya: Create rull variant
[coreboot2.git] / src / mainboard / prodrive / hermes / gpio.c
blob5cb901d8f478987629fcadac2b1ea62bdd5a7b15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <commonlib/helpers.h>
4 #include <intelblocks/gpio.h>
5 #include <soc/gpio.h>
7 #include "gpio.h"
9 /* Pad configuration in ramstage */
10 static const struct pad_config gpio_table[] = {
11 /* ------- GPIO Group GPP_A ------- */
13 /* ISH */
14 PAD_NC(GPP_A17, NONE),
15 PAD_NC(GPP_A18, NONE),
16 PAD_NC(GPP_A19, NONE),
17 PAD_NC(GPP_A20, NONE),
18 PAD_NC(GPP_A21, NONE),
19 PAD_NC(GPP_A22, NONE),
20 PAD_NC(GPP_A23, NONE),
22 /* ------- GPIO Group GPP_B ------- */
23 PAD_NC(GPP_B0, NONE),
24 PAD_NC(GPP_B1, NONE),
26 /* GPP_B2 - M2_E_BT_UART_WAKE_n */
27 PAD_CFG_GPI_INT(GPP_B2, NONE, DEEP, OFF),
29 /* GPP_B3 - PCH_M2_E_BT_KILL_n : handled at runtime */
30 /* GPP_B4 - PCH_M2_E_WLAN_KILL_n : handled at runtime */
32 /* SRCCLKREQ0# - SRCCLKREQ5# */
33 PAD_NC(GPP_B5, NONE),
34 PAD_NC(GPP_B6, NONE),
35 PAD_NC(GPP_B7, NONE),
36 PAD_NC(GPP_B8, NONE),
37 PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* M2_M_CLK_REQ_n */
38 PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* M2_E_CLK_REQ_n */
40 PAD_NC(GPP_B11, NONE),
42 /* GPP_B12 - SLP_S0_n */
43 PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
44 /* GPP_B13 - PLTRST_n */
45 PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
47 /* GPP_B14 - SPKR */
48 PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
50 /* GSPI0 */
51 PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI0_CS */
52 PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI0_CLK */
53 PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI0_MISO */
54 PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* SPI0_MOSI */
56 /* GSPI1 */
57 PAD_NC(GPP_B19, NONE),
58 PAD_NC(GPP_B20, NONE),
59 PAD_NC(GPP_B21, NONE),
60 PAD_NC(GPP_B22, NONE),
62 PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* PCH_SML1_ALERT_n */
64 /* ------- GPIO Group GPP_C ------- */
65 /* SML0 - Used by CSME */
66 PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PCH_SML0_CLK */
67 PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PCH_SML0_DATA */
68 PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* PCH_SML0_ALERT_N */
70 /* SML1 - Used by CSME */
71 PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PCH_SML1_CLK */
72 PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PCH_SML1_DATA */
74 /* UART0 */
75 PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */
76 PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */
77 PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* UART0_RTS_N */
78 PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* UART0_CTS_N */
80 /* UART1 */
81 PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */
82 PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */
83 PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* UART1_RTS_N */
84 PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* UART1_CTS_N */
86 PAD_NC(GPP_C17, NONE),
88 PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), /* AUD_FPA_PRSNT_n */
89 /* GPP_C19 - AUD_AMP_EN : configured at runtime */
91 /* UART2 */
92 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
93 PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
94 PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* UART2_RTS_N */
95 PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* UART2_CTS_N */
97 /* ------- GPIO Group GPP_D ------- */
98 /* SPI1 */
99 PAD_NC(GPP_D0, NONE),
100 PAD_NC(GPP_D1, NONE),
101 PAD_NC(GPP_D2, NONE),
102 PAD_NC(GPP_D3, NONE),
104 PAD_NC(GPP_D4, NONE),
106 /* CNVi */
107 PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), /* M2_E_BT_PCMFRM_CRF_RST_n */
108 PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), /* M2_E_BT_PCMOUT_CLKREQ0 */
109 PAD_NC(GPP_D7, NONE), /* M2_E_BT_PCMIN */
110 PAD_NC(GPP_D8, NONE), /* M2_E_BT_PCMCLK */
112 /* ISH SPI */
113 PAD_NC(GPP_D9, NONE),
114 PAD_NC(GPP_D10, NONE),
115 PAD_NC(GPP_D11, NONE),
116 PAD_NC(GPP_D12, NONE),
118 /* ISH UART */
119 PAD_NC(GPP_D13, NONE),
120 PAD_NC(GPP_D14, NONE),
121 PAD_NC(GPP_D15, NONE),
122 PAD_NC(GPP_D16, NONE),
124 /* DMIC */
125 PAD_NC(GPP_D17, NONE),
126 PAD_NC(GPP_D18, NONE),
127 PAD_NC(GPP_D19, NONE),
128 PAD_NC(GPP_D20, NONE),
130 PAD_NC(GPP_D21, NONE),
131 PAD_NC(GPP_D22, NONE),
132 PAD_NC(GPP_D23, NONE),
134 /* ------- GPIO Group GPP_G ------- */
135 /* GPP_G0 - USB31_RP1_PWR_EN : configured at runtime */
136 /* GPP_G1 - USB31_RP2_PWR_EN : configured at runtime */
137 /* GPP_G2 - USB31_FP_PWR_EN : configured at runtime */
138 /* GPP_G3 - USB2_FP1_PWR_EN : configured at runtime */
139 /* GPP_G4 - USB2_FP2_PWR_EN : configured at runtime */
141 PAD_NC(GPP_G5, NONE),
142 PAD_NC(GPP_G6, NONE),
143 PAD_NC(GPP_G7, NONE),
145 /* ------- GPIO Group GPD ------- */
146 /* GPD0 - BATLOW */
147 PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
148 /* GPD1 - ACPRESENT */
149 PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
150 /* GPD2 - LAN_WAKE# */
151 PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
152 /* GPD3 - PRWBTN# */
153 PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
154 /* GPD4 - SLP_S3# */
155 PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
156 /* GPD5 - SLP_S4# */
157 PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
158 /* GPD6 - SLP_A# */
159 PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
160 /* GPD7 - GPIO */
161 PAD_NC(GPD7, NONE),
162 /* GPD8 - SUSCLK */
163 PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
164 /* GPD9 - SLP_WLAN */
165 PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
166 /* GPD10 - SLP_S5# */
167 PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
168 /* GPD11 - LAN_DISABLE_n */
169 PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
171 /* ------- GPIO Group GPP_K ------- */
172 /* GPP_K0 - PERST_PCH_SLOTS_n : configured at runtime */
173 /* GPP_K1 - PERST_CPU_SLOTS_n : configured at runtime */
174 /* GPP_K2 - PERST_CNVI_SLOTS_n : configured at runtime */
175 /* GPP_K3 - DP1_PWR_EN : configured at runtime */
176 /* GPP_K4 - DP2_PWR_EN : configured at runtime */
177 /* GPP_K5 - DP3_PWR_EN : configured at runtime */
179 PAD_NC(GPP_K6, NONE),
181 /* GPP_K7 - EN_3V3_KEYM_PCH : configured at runtime */
183 PAD_NC(GPP_K8, NONE),
184 PAD_NC(GPP_K9, NONE),
185 PAD_NC(GPP_K10, NONE),
186 PAD_NC(GPP_K11, NONE),
188 /* K12 - K16 in early GPIO config */
190 PAD_NC(GPP_K17, NONE),
192 /* GPP_K18/!NMI - NC */
193 PAD_NC(GPP_K18, NONE),
194 /* GPP_K19/!SMI - NC */
195 PAD_NC(GPP_K19, NONE),
197 /* GPP_K20 - CPU_CATERR_PCH_n */
198 PAD_CFG_GPI(GPP_K20, NONE, DEEP),
199 /* GPP_K21 - TPM_INT_n */
200 PAD_CFG_GPI_INT(GPP_K21, NONE, DEEP, OFF), /* Trigger? */
201 /* GPP_K22 - NC */
202 PAD_NC(GPP_K22, NONE),
203 /* GPP_K23 - NC */
204 PAD_NC(GPP_K23, NONE),
206 /* ------- GPIO Group GPP_H ------- */
208 /* SRCCLKREQ6# - SRCCLKREQ10# not used as CLKREQ, external 10K pullup */
209 PAD_CFG_GPI(GPP_H0, NONE, DEEP), /* PCIE_SLOT1_PRSNT_PCH_n */
210 PAD_CFG_GPI(GPP_H1, NONE, DEEP), /* PCIE_SLOT2_PRSNT_PCH_n */
211 PAD_CFG_GPI(GPP_H2, NONE, DEEP), /* PCIE_SLOT3_PRSNT_PCH_n */
212 PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* PCIE_SLOT4_PRSNT_PCH_n */
213 PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */
215 PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */
217 /* GPP_H5 - PCH_HBLED_n configured in early init */
219 /* SRCCLKREQ13# - SRCCLKREQ15# */
220 PAD_NC(GPP_H7, NONE),
221 PAD_NC(GPP_H8, NONE),
222 PAD_NC(GPP_H9, NONE),
224 /* SML2 - Used by CSME */
225 PAD_NC(GPP_H10, NONE),
226 PAD_NC(GPP_H11, NONE),
227 PAD_NC(GPP_H12, NONE),
229 /* SML3 - Used by CSME */
230 PAD_NC(GPP_H13, NONE),
231 PAD_NC(GPP_H14, NONE),
232 PAD_NC(GPP_H15, NONE),
234 /* SML4 - Used by CSME */
235 PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* PCIE_SMB_CLK */
236 PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* PCIE_SMB_DATA */
237 PAD_NC(GPP_H18, NONE),
239 /* ISH I2C0 */
240 PAD_NC(GPP_H19, NONE),
241 PAD_NC(GPP_H20, NONE),
243 /* ISH I2C1 */
244 PAD_NC(GPP_H21, NONE),
245 PAD_NC(GPP_H22, NONE),
247 PAD_NC(GPP_H23, NONE),
249 /* ------- GPIO Group GPP_E ------- */
250 /* GPP_E0 - NC */
251 PAD_NC(GPP_E0, NONE),
252 /* GPP_E1 - M2_SATA_PCIE_SEL */
253 PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
254 /* GPP_E2 - NC */
255 PAD_NC(GPP_E2, NONE),
256 /* GPP_E3 - NC */
257 PAD_NC(GPP_E3, NONE),
258 /* GPP_E4 - NC */
259 PAD_NC(GPP_E4, NONE),
261 /* GPP_E5 - PCH_M2_SATA_DEVSLP1 */
262 PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
263 /* GPP_E6 - NC */
264 PAD_NC(GPP_E6, NONE),
265 /* GPP_E8 - SATALED# */
266 PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
268 /* GPP_E9 - USB31_RP1_OC_N */
269 PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
270 /* GPP_E10 - USB31_RP2_OC_N */
271 PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
272 /* GPP_E11 - USB31_FP_OC_N */
273 PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
274 /* GPP_E12 - USB2_FP1_OC_N */
275 PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
277 /* ------- GPIO Group GPP_F ------- */
278 /* SATAGP3-7 */
279 PAD_NC(GPP_F0, NONE),
280 PAD_NC(GPP_F1, NONE),
281 PAD_NC(GPP_F2, NONE),
282 PAD_NC(GPP_F3, NONE),
283 PAD_NC(GPP_F4, NONE),
285 /* SATA DEVSLP3-7 */
286 PAD_NC(GPP_F5, NONE),
287 PAD_NC(GPP_F6, NONE),
288 PAD_NC(GPP_F7, NONE),
289 PAD_NC(GPP_F8, NONE),
290 PAD_NC(GPP_F9, NONE),
292 /* SGPIO has external 2K pullups */
293 /* GPP_F10 - SATA_SCLOCK */
294 PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
295 /* GPP_F11 - SATA_SLOAD */
296 PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
297 /* GPP_F12 - SATA_SDATAOUT1 */
298 PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
299 /* GPP_F13 - SATA_BMC_SDATAOUT0 */
300 PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
302 /* GPP_F14 - PS_ON_PCH_n */
303 PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2),
304 /* GPP_F15 - USB2_FP2_OC_N */
305 PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
307 /* GPP_F16 - NC/PU */
308 PAD_NC(GPP_F16, NONE),
309 /* GPP_F17 - GPIO */
310 PAD_NC(GPP_F17, NONE),
311 /* GPP_F18 - GPIO */
312 PAD_NC(GPP_F18, NONE),
313 /* GPP_F19 - GPIO */
314 PAD_NC(GPP_F19, NONE),
315 /* GPP_F20 - GPIO */
316 PAD_NC(GPP_F20, NONE),
317 /* GPP_F21 - GPIO */
318 PAD_NC(GPP_F21, NONE),
319 /* GPP_F22 - GPIO */
320 PAD_NC(GPP_F22, NONE),
321 /* GPP_F23 - NC */
322 PAD_NC(GPP_F23, NONE),
323 /* GPP_J0 - CNV_GNSS_PA_BLANKING */
324 PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
325 /* GPP_J1 - NC */
326 PAD_NC(GPP_J1, NONE),
327 /* GPP_J2 - NC */
328 PAD_NC(GPP_J2, NONE),
329 /* GPP_J3 - NC */
330 PAD_NC(GPP_J3, NONE),
332 /* CNVi */
333 /* GPP_J4 - CNV_BRI_DT*/
334 PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
335 /* GPP_J5 - CNV_BRI_RSP */
336 PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
337 /* GPP_J6 - CNV_RGI_DT */
338 PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
339 /* GPP_J7 - CNV_RGI_RSP */
340 PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
341 /* GPP_J8 - CNV_MFUART2_RXD */
342 PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
343 /* GPP_J9 - CNV_MFUART2_TXD */
344 PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
346 PAD_NC(GPP_J10, NONE),
347 PAD_NC(GPP_J11, NONE),
349 /* Display Port */
350 PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DP1_HPD */
351 PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DP2_HPD */
352 PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), /* DP3_HPD */
353 PAD_NC(GPP_I3, NONE),
354 PAD_NC(GPP_I4, NONE),
356 PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* DP1_DDC_SCL */
357 PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* DP1_DDC_SDA */
359 PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* DP2_DDC_SCL */
360 PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* DP2_DDC_SDA */
362 PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* DP3_DDC_SCL */
363 PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* DP3_DDC_SDA */
365 PAD_NC(GPP_I11, NONE),
366 PAD_NC(GPP_I12, NONE),
367 PAD_NC(GPP_I13, NONE),
368 PAD_NC(GPP_I14, NONE),
372 /* Early pad configuration in bootblock */
373 const struct pad_config early_gpio_table[] = {
374 /* Get PCIe out of reset */
375 PAD_CFG_GPO(GPP_K0, 1, DEEP), /* PERST_PCH_SLOTS_n */
376 PAD_CFG_GPO(GPP_K1, 1, DEEP), /* PERST_CPU_SLOTS_n */
377 PAD_CFG_GPO(GPP_K2, 1, DEEP), /* PERST_CNVI_SLOTS_n */
379 /* SMB */
380 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_SMB_CLK */
381 PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_SMB_DATA */
382 PAD_NC(GPP_C2, NONE),
384 /* BMC HSI */
385 PAD_CFG_GPI(GPP_K12, NONE, DEEP), /* PCH_IO_2 */
386 PAD_CFG_GPI(GPP_K13, NONE, DEEP), /* PCH_IO_3 */
387 PAD_CFG_GPI(GPP_K14, NONE, DEEP), /* PCH_IO_1 */
388 PAD_NC(GPP_K15, NONE),
389 PAD_CFG_GPI(GPP_K16, NONE, DEEP), /* PCH_IO_0 */
391 /* LED */
392 PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */
394 /* UART0 */
395 PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */
396 PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */
398 /* UART1 */
399 PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */
400 PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */
402 /* UART2 */
403 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
404 PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
407 void program_gpio_pads(void)
409 gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
412 void program_early_gpio_pads(void)
414 gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));