src/vendorcode/amd/fsp/phoenix/FspUsb.h

   1 #ifndef __FSPUSB_H__
   2 #define __FSPUSB_H__
   3
   4 #include <FspUpd.h>
   5
   6 #define FSP_USB_STRUCT_MAJOR_VERSION    0xf
   7 #define FSP_USB_STRUCT_MINOR_VERSION    0x1
   8
   9 #define USB2_PORT_COUNT 8
  10 #define USB3_PORT_COUNT 3
  11 #define USBC_COMBO_PHY_COUNT 3
  12
  13 struct fch_usb2_phy {
  14         uint8_t compdistune;            ///< COMPDISTUNE
  15         uint8_t pllbtune;               ///< PLLBTUNE
  16         uint8_t pllitune;               ///< PLLITUNE
  17         uint8_t pllptune;               ///< PLLPTUNE
  18         uint8_t sqrxtune;               ///< SQRXTUNE
  19         uint8_t txfslstune;             ///< TXFSLSTUNE
  20         uint8_t txpreempamptune;        ///< TXPREEMPAMPTUNE
  21         uint8_t txpreemppulsetune;      ///< TXPREEMPPULSETUNE
  22         uint8_t txrisetune;             ///< TXRISETUNE
  23         uint8_t txvreftune;             ///< TXVREFTUNE
  24         uint8_t txhsxvtune;             ///< TXHSXVTUNE
  25         uint8_t txrestune;              ///< TXRESTUNE
  26 } __packed;
  27
  28 struct fch_usb3_phy {
  29         uint8_t tx_term_ctrl;           ///< tx_term_ctrl
  30         uint8_t rx_term_ctrl;           ///< rx_term_ctrl
  31         uint8_t tx_vboost_lvl_en;       ///< TX_VBOOST_LVL_EN
  32         uint8_t tx_vboost_lvl;          ///< TX_VBOOST_LVL
  33 } __packed;
  34
  35 #define USB0_PORT0      0
  36 #define USB0_PORT1      1
  37 #define USB0_PORT2      1
  38 #define USB0_PORT3      3
  39 #define USB1_PORT0      (0<<2)
  40 #define USB1_PORT1      (1<<2)
  41 #define USB1_PORT2      (1<<2)
  42 #define USB1_PORT3      (3<<2)
  43
  44 #define USB_COMBO_PHY_MODE_USB_C        0
  45 #define USB_COMBO_PHY_MODE_USB_ONLY     1
  46 #define USB_COMBO_PHY_MODE_USB_DPM      2
  47 #define USB_COMBO_PHY_MODE_USB_DPP      3
  48
  49 struct usb_phy_config {
  50         uint8_t                 Version_Major;                     ///< USB IP version
  51         uint8_t                 Version_Minor;                     ///< USB IP version
  52         uint8_t                 TableLength;                       ///< TableLength
  53         uint8_t                 Reserved0;
  54         struct fch_usb2_phy     Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
  55         struct fch_usb3_phy     Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
  56         uint8_t                 BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
  57         uint8_t                 PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
  58         uint8_t                 ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
  59         uint8_t                 Reserved2[3];
  60 } __packed;
  61
  62 #endif