| commit | 00b0285b36644d6c4c64b0c28782db1962fc4568 | |
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | |
| Thu, 14 Nov 2024 10:53:43 +0000 (14 11:53 +0100) | ||
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | |
| Mon, 18 Nov 2024 10:27:54 +0000 (18 10:27 +0000) | ||
| tree | d59d5ddad4cf315c501cf1b0727af2c5e1ccd6e5 | treesnapshot (tar.gz zip) |
| parent | d1dac66e617ab3ae91c4d602444d552f4e627ffa | commitdiff |
mb/ocp/tiogapass: Fix GPIOs
Do not enable SMIs on GPIOs since there's no SMI handler.
Without an SMI handler this will just slow down the platform once
the SMI asserts since it's never cleared. Once the protocol between
BMC and x86 has been implemented in an SMI handler, this can be reverted.
TEST: Booted on OCP/tiogapass without massive slowdown when SMIs are enabled.
Change-Id: If16c2c427f9b160f78a768a01a60128a6ed2c53f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Do not enable SMIs on GPIOs since there's no SMI handler.
Without an SMI handler this will just slow down the platform once
the SMI asserts since it's never cleared. Once the protocol between
BMC and x86 has been implemented in an SMI handler, this can be reverted.
TEST: Booted on OCP/tiogapass without massive slowdown when SMIs are enabled.
Change-Id: If16c2c427f9b160f78a768a01a60128a6ed2c53f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
| src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h | diffblobblamehistory |