| commit | 6cb6bfff381111956c43f9509ee6f5141ec67c91 | |
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | |
| Fri, 19 Jan 2024 14:44:36 +0000 (19 15:44 +0100) | ||
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | |
| Tue, 5 Mar 2024 11:24:38 +0000 (5 11:24 +0000) | ||
| tree | b27c78b97c64b921293c377ba0577744f9aa52a7 | treesnapshot (tar.gz zip) |
| parent | 3b0d573dc24f145a0c4bac42a973386cc9aa5d42 | commitdiff |
soc/intel/xeon_sp/util: Enhance lock_pam0123
- Only compile code in ramstage
- Lock PAM on all sockets
- Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
- Only compile code in ramstage
- Lock PAM on all sockets
- Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>