soc/intel/xeon_sp: Initial support for PCI multi segment groups
commit8061957cc12769714e7041093c065c6d6d212249
authorPatrick Rudolph <patrick.rudolph@9elements.com>
Tue, 12 Mar 2024 17:32:35 +0000 (12 18:32 +0100)
committerArthur Heymans <arthur@aheymans.xyz>
Tue, 19 Mar 2024 09:56:49 +0000 (19 09:56 +0000)
tree40379a2ac52cd0ab971852394d9d01cf1181728e
parentd425e881e339e8f92c48237d1e212275c5a7cdc3
soc/intel/xeon_sp: Initial support for PCI multi segment groups

Add PCI enumeration support by reading the PCIeSegment reported in the
FSP HOB and add it when creating the PCI domain for each stack.

The PCI enumeration will be able to scan the additional PCI segment
groups and properly handle those devices.

TEST=Booted on ibm/sbp1 with multiple PCI segment groups enabled
      to ubuntu 22.04.
TEST=intel/archercity CRB

Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79878
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
src/soc/intel/xeon_sp/chip_common.c
src/soc/intel/xeon_sp/include/soc/chip_common.h
src/soc/intel/xeon_sp/spr/ioat.c