From e4b2f3a6a2ecae9375f3014461b989e629d83410 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 28 Apr 2024 11:18:43 +0200 Subject: [PATCH] mb/lenovo/*: Set VR12 PSI to fix crash When in Package C3 or deeper the PSI settings are used to switch the CPU VR into a low power state. It was found that the voltage regulator on the Sandy-Bridge series has non-default PSI settings, compared to Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3 as the vendor BIOS does to fix a hang when the package is idle. Since neither the vendor BIOS is open-source, nor datasheet exists for the used VR it's unclear why those PSI values must be used and how they influence the regulator. The X220 already has the correct PSI values configured and is now stable for more than 24h in Package C7 state. TEST: Not tested on the affected boards, only checked vendor firmware. Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/82070 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/mainboard/lenovo/l520/devicetree.cb | 9 ++++++++- src/mainboard/lenovo/t420/devicetree.cb | 9 ++++++++- src/mainboard/lenovo/t420s/devicetree.cb | 9 ++++++++- src/mainboard/lenovo/t520/devicetree.cb | 8 ++++++++ 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ead7e0bb87..a4fbe11ee8 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -12,7 +12,14 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21dd inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index d4b31afe88..d469da6b79 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index fb309170fe..4ce90772a5 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a2e12c34d7..5edb63e95d 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,6 +15,14 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21cf inherit -- 2.11.4.GIT