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blk: rq_data_dir() should not return a boolean
[cris-mirror.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blobdc55f8dedf2c6bb597bddd858d9acd960398fceb
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22
23 #include <linux/omap-dma.h>
24 #include "l3_3xxx.h"
25 #include "l4_3xxx.h"
26 #include <linux/platform_data/asoc-ti-mcbsp.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <linux/platform_data/mailbox-omap.h>
30 #include <plat/dmtimer.h>
31
32 #include "soc.h"
33 #include "omap_hwmod.h"
34 #include "omap_hwmod_common_data.h"
35 #include "prm-regbits-34xx.h"
36 #include "cm-regbits-34xx.h"
37
38 #include "i2c.h"
39 #include "wd_timer.h"
40 #include "serial.h"
41
42 /*
43 * OMAP3xxx hardware module integration data
44 *
45 * All of the data in this section should be autogeneratable from the
46 * TI hardware database or other technical documentation. Data that
47 * is driver-specific or driver-kernel integration-specific belongs
48 * elsewhere.
49 */
50
51 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
52
53 /*
54 * IP blocks
55 */
56
57 /* L3 */
58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
59 { .irq = 9 + OMAP_INTC_START, },
60 { .irq = 10 + OMAP_INTC_START, },
61 { .irq = -1 },
62 };
63
64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
65 .name = "l3_main",
66 .class = &l3_hwmod_class,
67 .mpu_irqs = omap3xxx_l3_main_irqs,
68 .flags = HWMOD_NO_IDLEST,
69 };
70
71 /* L4 CORE */
72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
73 .name = "l4_core",
74 .class = &l4_hwmod_class,
75 .flags = HWMOD_NO_IDLEST,
76 };
77
78 /* L4 PER */
79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
80 .name = "l4_per",
81 .class = &l4_hwmod_class,
82 .flags = HWMOD_NO_IDLEST,
83 };
84
85 /* L4 WKUP */
86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
87 .name = "l4_wkup",
88 .class = &l4_hwmod_class,
89 .flags = HWMOD_NO_IDLEST,
90 };
91
92 /* L4 SEC */
93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
94 .name = "l4_sec",
95 .class = &l4_hwmod_class,
96 .flags = HWMOD_NO_IDLEST,
97 };
98
99 /* MPU */
100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
101 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
102 { .irq = -1 }
103 };
104
105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
106 .name = "mpu",
107 .mpu_irqs = omap3xxx_mpu_irqs,
108 .class = &mpu_hwmod_class,
109 .main_clk = "arm_fck",
110 };
111
112 /* IVA2 (IVA2) */
113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
114 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
117 };
118
119 static struct omap_hwmod omap3xxx_iva_hwmod = {
120 .name = "iva",
121 .class = &iva_hwmod_class,
122 .clkdm_name = "iva2_clkdm",
123 .rst_lines = omap3xxx_iva_resets,
124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
125 .main_clk = "iva2_ck",
126 .prcm = {
127 .omap2 = {
128 .module_offs = OMAP3430_IVA2_MOD,
129 .prcm_reg_id = 1,
130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
131 .idlest_reg_id = 1,
132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
133 }
134 },
135 };
136
137 /*
138 * 'debugss' class
139 * debug and emulation sub system
140 */
141
142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
143 .name = "debugss",
144 };
145
146 /* debugss */
147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
148 .name = "debugss",
149 .class = &omap3xxx_debugss_hwmod_class,
150 .clkdm_name = "emu_clkdm",
151 .main_clk = "emu_src_ck",
152 .flags = HWMOD_NO_IDLEST,
153 };
154
155 /* timer class */
156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
157 .rev_offs = 0x0000,
158 .sysc_offs = 0x0010,
159 .syss_offs = 0x0014,
160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
166 .sysc_fields = &omap_hwmod_sysc_type1,
167 };
168
169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
170 .name = "timer",
171 .sysc = &omap3xxx_timer_sysc,
172 };
173
174 /* secure timers dev attribute */
175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
177 };
178
179 /* always-on timers dev attribute */
180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
181 .timer_capability = OMAP_TIMER_ALWON,
182 };
183
184 /* pwm timers dev attribute */
185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
186 .timer_capability = OMAP_TIMER_HAS_PWM,
187 };
188
189 /* timers with DSP interrupt dev attribute */
190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
192 };
193
194 /* pwm timers with DSP interrupt dev attribute */
195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
197 };
198
199 /* timer1 */
200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
201 .name = "timer1",
202 .mpu_irqs = omap2_timer1_mpu_irqs,
203 .main_clk = "gpt1_fck",
204 .prcm = {
205 .omap2 = {
206 .prcm_reg_id = 1,
207 .module_bit = OMAP3430_EN_GPT1_SHIFT,
208 .module_offs = WKUP_MOD,
209 .idlest_reg_id = 1,
210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
211 },
212 },
213 .dev_attr = &capability_alwon_dev_attr,
214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
216 };
217
218 /* timer2 */
219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
220 .name = "timer2",
221 .mpu_irqs = omap2_timer2_mpu_irqs,
222 .main_clk = "gpt2_fck",
223 .prcm = {
224 .omap2 = {
225 .prcm_reg_id = 1,
226 .module_bit = OMAP3430_EN_GPT2_SHIFT,
227 .module_offs = OMAP3430_PER_MOD,
228 .idlest_reg_id = 1,
229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
230 },
231 },
232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
234 };
235
236 /* timer3 */
237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
238 .name = "timer3",
239 .mpu_irqs = omap2_timer3_mpu_irqs,
240 .main_clk = "gpt3_fck",
241 .prcm = {
242 .omap2 = {
243 .prcm_reg_id = 1,
244 .module_bit = OMAP3430_EN_GPT3_SHIFT,
245 .module_offs = OMAP3430_PER_MOD,
246 .idlest_reg_id = 1,
247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
248 },
249 },
250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
252 };
253
254 /* timer4 */
255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
256 .name = "timer4",
257 .mpu_irqs = omap2_timer4_mpu_irqs,
258 .main_clk = "gpt4_fck",
259 .prcm = {
260 .omap2 = {
261 .prcm_reg_id = 1,
262 .module_bit = OMAP3430_EN_GPT4_SHIFT,
263 .module_offs = OMAP3430_PER_MOD,
264 .idlest_reg_id = 1,
265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
266 },
267 },
268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
270 };
271
272 /* timer5 */
273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
274 .name = "timer5",
275 .mpu_irqs = omap2_timer5_mpu_irqs,
276 .main_clk = "gpt5_fck",
277 .prcm = {
278 .omap2 = {
279 .prcm_reg_id = 1,
280 .module_bit = OMAP3430_EN_GPT5_SHIFT,
281 .module_offs = OMAP3430_PER_MOD,
282 .idlest_reg_id = 1,
283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
284 },
285 },
286 .dev_attr = &capability_dsp_dev_attr,
287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289 };
290
291 /* timer6 */
292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
293 .name = "timer6",
294 .mpu_irqs = omap2_timer6_mpu_irqs,
295 .main_clk = "gpt6_fck",
296 .prcm = {
297 .omap2 = {
298 .prcm_reg_id = 1,
299 .module_bit = OMAP3430_EN_GPT6_SHIFT,
300 .module_offs = OMAP3430_PER_MOD,
301 .idlest_reg_id = 1,
302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
303 },
304 },
305 .dev_attr = &capability_dsp_dev_attr,
306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
308 };
309
310 /* timer7 */
311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
312 .name = "timer7",
313 .mpu_irqs = omap2_timer7_mpu_irqs,
314 .main_clk = "gpt7_fck",
315 .prcm = {
316 .omap2 = {
317 .prcm_reg_id = 1,
318 .module_bit = OMAP3430_EN_GPT7_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
320 .idlest_reg_id = 1,
321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
322 },
323 },
324 .dev_attr = &capability_dsp_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
327 };
328
329 /* timer8 */
330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
331 .name = "timer8",
332 .mpu_irqs = omap2_timer8_mpu_irqs,
333 .main_clk = "gpt8_fck",
334 .prcm = {
335 .omap2 = {
336 .prcm_reg_id = 1,
337 .module_bit = OMAP3430_EN_GPT8_SHIFT,
338 .module_offs = OMAP3430_PER_MOD,
339 .idlest_reg_id = 1,
340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
341 },
342 },
343 .dev_attr = &capability_dsp_pwm_dev_attr,
344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
346 };
347
348 /* timer9 */
349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
350 .name = "timer9",
351 .mpu_irqs = omap2_timer9_mpu_irqs,
352 .main_clk = "gpt9_fck",
353 .prcm = {
354 .omap2 = {
355 .prcm_reg_id = 1,
356 .module_bit = OMAP3430_EN_GPT9_SHIFT,
357 .module_offs = OMAP3430_PER_MOD,
358 .idlest_reg_id = 1,
359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
360 },
361 },
362 .dev_attr = &capability_pwm_dev_attr,
363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
365 };
366
367 /* timer10 */
368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
369 .name = "timer10",
370 .mpu_irqs = omap2_timer10_mpu_irqs,
371 .main_clk = "gpt10_fck",
372 .prcm = {
373 .omap2 = {
374 .prcm_reg_id = 1,
375 .module_bit = OMAP3430_EN_GPT10_SHIFT,
376 .module_offs = CORE_MOD,
377 .idlest_reg_id = 1,
378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
379 },
380 },
381 .dev_attr = &capability_pwm_dev_attr,
382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
384 };
385
386 /* timer11 */
387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
388 .name = "timer11",
389 .mpu_irqs = omap2_timer11_mpu_irqs,
390 .main_clk = "gpt11_fck",
391 .prcm = {
392 .omap2 = {
393 .prcm_reg_id = 1,
394 .module_bit = OMAP3430_EN_GPT11_SHIFT,
395 .module_offs = CORE_MOD,
396 .idlest_reg_id = 1,
397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
398 },
399 },
400 .dev_attr = &capability_pwm_dev_attr,
401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
403 };
404
405 /* timer12 */
406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
407 { .irq = 95 + OMAP_INTC_START, },
408 { .irq = -1 },
409 };
410
411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
412 .name = "timer12",
413 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
414 .main_clk = "gpt12_fck",
415 .prcm = {
416 .omap2 = {
417 .prcm_reg_id = 1,
418 .module_bit = OMAP3430_EN_GPT12_SHIFT,
419 .module_offs = WKUP_MOD,
420 .idlest_reg_id = 1,
421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
422 },
423 },
424 .dev_attr = &capability_secure_dev_attr,
425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
427 };
428
429 /*
430 * 'wd_timer' class
431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
432 * overflow condition
433 */
434
435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
436 .rev_offs = 0x0000,
437 .sysc_offs = 0x0010,
438 .syss_offs = 0x0014,
439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444 .sysc_fields = &omap_hwmod_sysc_type1,
445 };
446
447 /* I2C common */
448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
449 .rev_offs = 0x00,
450 .sysc_offs = 0x20,
451 .syss_offs = 0x10,
452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
456 .clockact = CLOCKACT_TEST_ICLK,
457 .sysc_fields = &omap_hwmod_sysc_type1,
458 };
459
460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
461 .name = "wd_timer",
462 .sysc = &omap3xxx_wd_timer_sysc,
463 .pre_shutdown = &omap2_wd_timer_disable,
464 .reset = &omap2_wd_timer_reset,
465 };
466
467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
468 .name = "wd_timer2",
469 .class = &omap3xxx_wd_timer_hwmod_class,
470 .main_clk = "wdt2_fck",
471 .prcm = {
472 .omap2 = {
473 .prcm_reg_id = 1,
474 .module_bit = OMAP3430_EN_WDT2_SHIFT,
475 .module_offs = WKUP_MOD,
476 .idlest_reg_id = 1,
477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
478 },
479 },
480 /*
481 * XXX: Use software supervised mode, HW supervised smartidle seems to
482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
483 */
484 .flags = HWMOD_SWSUP_SIDLE,
485 };
486
487 /* UART1 */
488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
489 .name = "uart1",
490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck",
493 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
494 .prcm = {
495 .omap2 = {
496 .module_offs = CORE_MOD,
497 .prcm_reg_id = 1,
498 .module_bit = OMAP3430_EN_UART1_SHIFT,
499 .idlest_reg_id = 1,
500 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
501 },
502 },
503 .class = &omap2_uart_class,
504 };
505
506 /* UART2 */
507 static struct omap_hwmod omap3xxx_uart2_hwmod = {
508 .name = "uart2",
509 .mpu_irqs = omap2_uart2_mpu_irqs,
510 .sdma_reqs = omap2_uart2_sdma_reqs,
511 .main_clk = "uart2_fck",
512 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
513 .prcm = {
514 .omap2 = {
515 .module_offs = CORE_MOD,
516 .prcm_reg_id = 1,
517 .module_bit = OMAP3430_EN_UART2_SHIFT,
518 .idlest_reg_id = 1,
519 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
520 },
521 },
522 .class = &omap2_uart_class,
523 };
524
525 /* UART3 */
526 static struct omap_hwmod omap3xxx_uart3_hwmod = {
527 .name = "uart3",
528 .mpu_irqs = omap2_uart3_mpu_irqs,
529 .sdma_reqs = omap2_uart3_sdma_reqs,
530 .main_clk = "uart3_fck",
531 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
532 HWMOD_SWSUP_SIDLE,
533 .prcm = {
534 .omap2 = {
535 .module_offs = OMAP3430_PER_MOD,
536 .prcm_reg_id = 1,
537 .module_bit = OMAP3430_EN_UART3_SHIFT,
538 .idlest_reg_id = 1,
539 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
540 },
541 },
542 .class = &omap2_uart_class,
543 };
544
545 /* UART4 */
546 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
547 { .irq = 80 + OMAP_INTC_START, },
548 { .irq = -1 },
549 };
550
551 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
552 { .name = "rx", .dma_req = 82, },
553 { .name = "tx", .dma_req = 81, },
554 { .dma_req = -1 }
555 };
556
557 static struct omap_hwmod omap36xx_uart4_hwmod = {
558 .name = "uart4",
559 .mpu_irqs = uart4_mpu_irqs,
560 .sdma_reqs = uart4_sdma_reqs,
561 .main_clk = "uart4_fck",
562 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
563 .prcm = {
564 .omap2 = {
565 .module_offs = OMAP3430_PER_MOD,
566 .prcm_reg_id = 1,
567 .module_bit = OMAP3630_EN_UART4_SHIFT,
568 .idlest_reg_id = 1,
569 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
570 },
571 },
572 .class = &omap2_uart_class,
573 };
574
575 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
576 { .irq = 84 + OMAP_INTC_START, },
577 { .irq = -1 },
578 };
579
580 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
581 { .name = "rx", .dma_req = 55, },
582 { .name = "tx", .dma_req = 54, },
583 { .dma_req = -1 }
584 };
585
586 /*
587 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
588 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
589 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
590 * should not be needed. The functional clock structure of the AM35xx
591 * UART4 is extremely unclear and opaque; it is unclear what the role
592 * of uart1/2_fck is for the UART4. Any clarification from either
593 * empirical testing or the AM3505/3517 hardware designers would be
594 * most welcome.
595 */
596 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
597 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
598 };
599
600 static struct omap_hwmod am35xx_uart4_hwmod = {
601 .name = "uart4",
602 .mpu_irqs = am35xx_uart4_mpu_irqs,
603 .sdma_reqs = am35xx_uart4_sdma_reqs,
604 .main_clk = "uart4_fck",
605 .prcm = {
606 .omap2 = {
607 .module_offs = CORE_MOD,
608 .prcm_reg_id = 1,
609 .module_bit = AM35XX_EN_UART4_SHIFT,
610 .idlest_reg_id = 1,
611 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
612 },
613 },
614 .opt_clks = am35xx_uart4_opt_clks,
615 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
616 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
617 .class = &omap2_uart_class,
618 };
619
620 static struct omap_hwmod_class i2c_class = {
621 .name = "i2c",
622 .sysc = &i2c_sysc,
623 .rev = OMAP_I2C_IP_VERSION_1,
624 .reset = &omap_i2c_reset,
625 };
626
627 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
628 { .name = "dispc", .dma_req = 5 },
629 { .name = "dsi1", .dma_req = 74 },
630 { .dma_req = -1 }
631 };
632
633 /* dss */
634 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
635 /*
636 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
637 * driver does not use these clocks.
638 */
639 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
640 { .role = "tv_clk", .clk = "dss_tv_fck" },
641 /* required only on OMAP3430 */
642 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
643 };
644
645 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
646 .name = "dss_core",
647 .class = &omap2_dss_hwmod_class,
648 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
649 .sdma_reqs = omap3xxx_dss_sdma_chs,
650 .prcm = {
651 .omap2 = {
652 .prcm_reg_id = 1,
653 .module_bit = OMAP3430_EN_DSS1_SHIFT,
654 .module_offs = OMAP3430_DSS_MOD,
655 .idlest_reg_id = 1,
656 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
657 },
658 },
659 .opt_clks = dss_opt_clks,
660 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
661 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
662 };
663
664 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
665 .name = "dss_core",
666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
667 .class = &omap2_dss_hwmod_class,
668 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
669 .sdma_reqs = omap3xxx_dss_sdma_chs,
670 .prcm = {
671 .omap2 = {
672 .prcm_reg_id = 1,
673 .module_bit = OMAP3430_EN_DSS1_SHIFT,
674 .module_offs = OMAP3430_DSS_MOD,
675 .idlest_reg_id = 1,
676 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
677 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
678 },
679 },
680 .opt_clks = dss_opt_clks,
681 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
682 };
683
684 /*
685 * 'dispc' class
686 * display controller
687 */
688
689 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
690 .rev_offs = 0x0000,
691 .sysc_offs = 0x0010,
692 .syss_offs = 0x0014,
693 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
694 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
695 SYSC_HAS_ENAWAKEUP),
696 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
697 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
698 .sysc_fields = &omap_hwmod_sysc_type1,
699 };
700
701 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
702 .name = "dispc",
703 .sysc = &omap3_dispc_sysc,
704 };
705
706 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
707 .name = "dss_dispc",
708 .class = &omap3_dispc_hwmod_class,
709 .mpu_irqs = omap2_dispc_irqs,
710 .main_clk = "dss1_alwon_fck",
711 .prcm = {
712 .omap2 = {
713 .prcm_reg_id = 1,
714 .module_bit = OMAP3430_EN_DSS1_SHIFT,
715 .module_offs = OMAP3430_DSS_MOD,
716 },
717 },
718 .flags = HWMOD_NO_IDLEST,
719 .dev_attr = &omap2_3_dss_dispc_dev_attr
720 };
721
722 /*
723 * 'dsi' class
724 * display serial interface controller
725 */
726
727 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
728 .name = "dsi",
729 };
730
731 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
732 { .irq = 25 + OMAP_INTC_START, },
733 { .irq = -1 },
734 };
735
736 /* dss_dsi1 */
737 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
738 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
739 };
740
741 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
742 .name = "dss_dsi1",
743 .class = &omap3xxx_dsi_hwmod_class,
744 .mpu_irqs = omap3xxx_dsi1_irqs,
745 .main_clk = "dss1_alwon_fck",
746 .prcm = {
747 .omap2 = {
748 .prcm_reg_id = 1,
749 .module_bit = OMAP3430_EN_DSS1_SHIFT,
750 .module_offs = OMAP3430_DSS_MOD,
751 },
752 },
753 .opt_clks = dss_dsi1_opt_clks,
754 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
755 .flags = HWMOD_NO_IDLEST,
756 };
757
758 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
759 { .role = "ick", .clk = "dss_ick" },
760 };
761
762 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
763 .name = "dss_rfbi",
764 .class = &omap2_rfbi_hwmod_class,
765 .main_clk = "dss1_alwon_fck",
766 .prcm = {
767 .omap2 = {
768 .prcm_reg_id = 1,
769 .module_bit = OMAP3430_EN_DSS1_SHIFT,
770 .module_offs = OMAP3430_DSS_MOD,
771 },
772 },
773 .opt_clks = dss_rfbi_opt_clks,
774 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
775 .flags = HWMOD_NO_IDLEST,
776 };
777
778 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
779 /* required only on OMAP3430 */
780 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
781 };
782
783 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
784 .name = "dss_venc",
785 .class = &omap2_venc_hwmod_class,
786 .main_clk = "dss_tv_fck",
787 .prcm = {
788 .omap2 = {
789 .prcm_reg_id = 1,
790 .module_bit = OMAP3430_EN_DSS1_SHIFT,
791 .module_offs = OMAP3430_DSS_MOD,
792 },
793 },
794 .opt_clks = dss_venc_opt_clks,
795 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
796 .flags = HWMOD_NO_IDLEST,
797 };
798
799 /* I2C1 */
800 static struct omap_i2c_dev_attr i2c1_dev_attr = {
801 .fifo_depth = 8, /* bytes */
802 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
803 };
804
805 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
806 .name = "i2c1",
807 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
808 .mpu_irqs = omap2_i2c1_mpu_irqs,
809 .sdma_reqs = omap2_i2c1_sdma_reqs,
810 .main_clk = "i2c1_fck",
811 .prcm = {
812 .omap2 = {
813 .module_offs = CORE_MOD,
814 .prcm_reg_id = 1,
815 .module_bit = OMAP3430_EN_I2C1_SHIFT,
816 .idlest_reg_id = 1,
817 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
818 },
819 },
820 .class = &i2c_class,
821 .dev_attr = &i2c1_dev_attr,
822 };
823
824 /* I2C2 */
825 static struct omap_i2c_dev_attr i2c2_dev_attr = {
826 .fifo_depth = 8, /* bytes */
827 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
828 };
829
830 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
831 .name = "i2c2",
832 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
833 .mpu_irqs = omap2_i2c2_mpu_irqs,
834 .sdma_reqs = omap2_i2c2_sdma_reqs,
835 .main_clk = "i2c2_fck",
836 .prcm = {
837 .omap2 = {
838 .module_offs = CORE_MOD,
839 .prcm_reg_id = 1,
840 .module_bit = OMAP3430_EN_I2C2_SHIFT,
841 .idlest_reg_id = 1,
842 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
843 },
844 },
845 .class = &i2c_class,
846 .dev_attr = &i2c2_dev_attr,
847 };
848
849 /* I2C3 */
850 static struct omap_i2c_dev_attr i2c3_dev_attr = {
851 .fifo_depth = 64, /* bytes */
852 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
853 };
854
855 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
856 { .irq = 61 + OMAP_INTC_START, },
857 { .irq = -1 },
858 };
859
860 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
861 { .name = "tx", .dma_req = 25 },
862 { .name = "rx", .dma_req = 26 },
863 { .dma_req = -1 }
864 };
865
866 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
867 .name = "i2c3",
868 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
869 .mpu_irqs = i2c3_mpu_irqs,
870 .sdma_reqs = i2c3_sdma_reqs,
871 .main_clk = "i2c3_fck",
872 .prcm = {
873 .omap2 = {
874 .module_offs = CORE_MOD,
875 .prcm_reg_id = 1,
876 .module_bit = OMAP3430_EN_I2C3_SHIFT,
877 .idlest_reg_id = 1,
878 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
879 },
880 },
881 .class = &i2c_class,
882 .dev_attr = &i2c3_dev_attr,
883 };
884
885 /*
886 * 'gpio' class
887 * general purpose io module
888 */
889
890 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
891 .rev_offs = 0x0000,
892 .sysc_offs = 0x0010,
893 .syss_offs = 0x0014,
894 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
895 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
896 SYSS_HAS_RESET_STATUS),
897 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
898 .sysc_fields = &omap_hwmod_sysc_type1,
899 };
900
901 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
902 .name = "gpio",
903 .sysc = &omap3xxx_gpio_sysc,
904 .rev = 1,
905 };
906
907 /* gpio_dev_attr */
908 static struct omap_gpio_dev_attr gpio_dev_attr = {
909 .bank_width = 32,
910 .dbck_flag = true,
911 };
912
913 /* gpio1 */
914 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
915 { .role = "dbclk", .clk = "gpio1_dbck", },
916 };
917
918 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
919 .name = "gpio1",
920 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
921 .mpu_irqs = omap2_gpio1_irqs,
922 .main_clk = "gpio1_ick",
923 .opt_clks = gpio1_opt_clks,
924 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
925 .prcm = {
926 .omap2 = {
927 .prcm_reg_id = 1,
928 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
929 .module_offs = WKUP_MOD,
930 .idlest_reg_id = 1,
931 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
932 },
933 },
934 .class = &omap3xxx_gpio_hwmod_class,
935 .dev_attr = &gpio_dev_attr,
936 };
937
938 /* gpio2 */
939 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
940 { .role = "dbclk", .clk = "gpio2_dbck", },
941 };
942
943 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
944 .name = "gpio2",
945 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
946 .mpu_irqs = omap2_gpio2_irqs,
947 .main_clk = "gpio2_ick",
948 .opt_clks = gpio2_opt_clks,
949 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
950 .prcm = {
951 .omap2 = {
952 .prcm_reg_id = 1,
953 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
954 .module_offs = OMAP3430_PER_MOD,
955 .idlest_reg_id = 1,
956 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
957 },
958 },
959 .class = &omap3xxx_gpio_hwmod_class,
960 .dev_attr = &gpio_dev_attr,
961 };
962
963 /* gpio3 */
964 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
965 { .role = "dbclk", .clk = "gpio3_dbck", },
966 };
967
968 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
969 .name = "gpio3",
970 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
971 .mpu_irqs = omap2_gpio3_irqs,
972 .main_clk = "gpio3_ick",
973 .opt_clks = gpio3_opt_clks,
974 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
975 .prcm = {
976 .omap2 = {
977 .prcm_reg_id = 1,
978 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
979 .module_offs = OMAP3430_PER_MOD,
980 .idlest_reg_id = 1,
981 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
982 },
983 },
984 .class = &omap3xxx_gpio_hwmod_class,
985 .dev_attr = &gpio_dev_attr,
986 };
987
988 /* gpio4 */
989 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
990 { .role = "dbclk", .clk = "gpio4_dbck", },
991 };
992
993 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
994 .name = "gpio4",
995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
996 .mpu_irqs = omap2_gpio4_irqs,
997 .main_clk = "gpio4_ick",
998 .opt_clks = gpio4_opt_clks,
999 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1000 .prcm = {
1001 .omap2 = {
1002 .prcm_reg_id = 1,
1003 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1004 .module_offs = OMAP3430_PER_MOD,
1005 .idlest_reg_id = 1,
1006 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1007 },
1008 },
1009 .class = &omap3xxx_gpio_hwmod_class,
1010 .dev_attr = &gpio_dev_attr,
1011 };
1012
1013 /* gpio5 */
1014 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1015 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1016 { .irq = -1 },
1017 };
1018
1019 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1020 { .role = "dbclk", .clk = "gpio5_dbck", },
1021 };
1022
1023 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1024 .name = "gpio5",
1025 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1026 .mpu_irqs = omap3xxx_gpio5_irqs,
1027 .main_clk = "gpio5_ick",
1028 .opt_clks = gpio5_opt_clks,
1029 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1030 .prcm = {
1031 .omap2 = {
1032 .prcm_reg_id = 1,
1033 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1034 .module_offs = OMAP3430_PER_MOD,
1035 .idlest_reg_id = 1,
1036 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1037 },
1038 },
1039 .class = &omap3xxx_gpio_hwmod_class,
1040 .dev_attr = &gpio_dev_attr,
1041 };
1042
1043 /* gpio6 */
1044 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1045 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1046 { .irq = -1 },
1047 };
1048
1049 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1050 { .role = "dbclk", .clk = "gpio6_dbck", },
1051 };
1052
1053 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1054 .name = "gpio6",
1055 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1056 .mpu_irqs = omap3xxx_gpio6_irqs,
1057 .main_clk = "gpio6_ick",
1058 .opt_clks = gpio6_opt_clks,
1059 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1060 .prcm = {
1061 .omap2 = {
1062 .prcm_reg_id = 1,
1063 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1064 .module_offs = OMAP3430_PER_MOD,
1065 .idlest_reg_id = 1,
1066 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1067 },
1068 },
1069 .class = &omap3xxx_gpio_hwmod_class,
1070 .dev_attr = &gpio_dev_attr,
1071 };
1072
1073 /* dma attributes */
1074 static struct omap_dma_dev_attr dma_dev_attr = {
1075 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1076 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1077 .lch_count = 32,
1078 };
1079
1080 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1081 .rev_offs = 0x0000,
1082 .sysc_offs = 0x002c,
1083 .syss_offs = 0x0028,
1084 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1085 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1086 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1087 SYSS_HAS_RESET_STATUS),
1088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1090 .sysc_fields = &omap_hwmod_sysc_type1,
1091 };
1092
1093 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1094 .name = "dma",
1095 .sysc = &omap3xxx_dma_sysc,
1096 };
1097
1098 /* dma_system */
1099 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1100 .name = "dma",
1101 .class = &omap3xxx_dma_hwmod_class,
1102 .mpu_irqs = omap2_dma_system_irqs,
1103 .main_clk = "core_l3_ick",
1104 .prcm = {
1105 .omap2 = {
1106 .module_offs = CORE_MOD,
1107 .prcm_reg_id = 1,
1108 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1109 .idlest_reg_id = 1,
1110 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1111 },
1112 },
1113 .dev_attr = &dma_dev_attr,
1114 .flags = HWMOD_NO_IDLEST,
1115 };
1116
1117 /*
1118 * 'mcbsp' class
1119 * multi channel buffered serial port controller
1120 */
1121
1122 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1123 .sysc_offs = 0x008c,
1124 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1125 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1126 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1127 .sysc_fields = &omap_hwmod_sysc_type1,
1128 .clockact = 0x2,
1129 };
1130
1131 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1132 .name = "mcbsp",
1133 .sysc = &omap3xxx_mcbsp_sysc,
1134 .rev = MCBSP_CONFIG_TYPE3,
1135 };
1136
1137 /* McBSP functional clock mapping */
1138 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1139 { .role = "pad_fck", .clk = "mcbsp_clks" },
1140 { .role = "prcm_fck", .clk = "core_96m_fck" },
1141 };
1142
1143 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1144 { .role = "pad_fck", .clk = "mcbsp_clks" },
1145 { .role = "prcm_fck", .clk = "per_96m_fck" },
1146 };
1147
1148 /* mcbsp1 */
1149 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1150 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1151 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1152 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1153 { .irq = -1 },
1154 };
1155
1156 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1157 .name = "mcbsp1",
1158 .class = &omap3xxx_mcbsp_hwmod_class,
1159 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1160 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1161 .main_clk = "mcbsp1_fck",
1162 .prcm = {
1163 .omap2 = {
1164 .prcm_reg_id = 1,
1165 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1166 .module_offs = CORE_MOD,
1167 .idlest_reg_id = 1,
1168 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1169 },
1170 },
1171 .opt_clks = mcbsp15_opt_clks,
1172 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1173 };
1174
1175 /* mcbsp2 */
1176 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1177 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1178 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1179 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1180 { .irq = -1 },
1181 };
1182
1183 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1184 .sidetone = "mcbsp2_sidetone",
1185 };
1186
1187 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1188 .name = "mcbsp2",
1189 .class = &omap3xxx_mcbsp_hwmod_class,
1190 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1191 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1192 .main_clk = "mcbsp2_fck",
1193 .prcm = {
1194 .omap2 = {
1195 .prcm_reg_id = 1,
1196 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1197 .module_offs = OMAP3430_PER_MOD,
1198 .idlest_reg_id = 1,
1199 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1200 },
1201 },
1202 .opt_clks = mcbsp234_opt_clks,
1203 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1204 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1205 };
1206
1207 /* mcbsp3 */
1208 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1209 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1210 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1211 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1212 { .irq = -1 },
1213 };
1214
1215 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1216 .sidetone = "mcbsp3_sidetone",
1217 };
1218
1219 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1220 .name = "mcbsp3",
1221 .class = &omap3xxx_mcbsp_hwmod_class,
1222 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1223 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1224 .main_clk = "mcbsp3_fck",
1225 .prcm = {
1226 .omap2 = {
1227 .prcm_reg_id = 1,
1228 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1229 .module_offs = OMAP3430_PER_MOD,
1230 .idlest_reg_id = 1,
1231 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1232 },
1233 },
1234 .opt_clks = mcbsp234_opt_clks,
1235 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1236 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1237 };
1238
1239 /* mcbsp4 */
1240 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1241 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1242 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1243 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1244 { .irq = -1 },
1245 };
1246
1247 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1248 { .name = "rx", .dma_req = 20 },
1249 { .name = "tx", .dma_req = 19 },
1250 { .dma_req = -1 }
1251 };
1252
1253 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1254 .name = "mcbsp4",
1255 .class = &omap3xxx_mcbsp_hwmod_class,
1256 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1257 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1258 .main_clk = "mcbsp4_fck",
1259 .prcm = {
1260 .omap2 = {
1261 .prcm_reg_id = 1,
1262 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1263 .module_offs = OMAP3430_PER_MOD,
1264 .idlest_reg_id = 1,
1265 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1266 },
1267 },
1268 .opt_clks = mcbsp234_opt_clks,
1269 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1270 };
1271
1272 /* mcbsp5 */
1273 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1274 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1275 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1276 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1277 { .irq = -1 },
1278 };
1279
1280 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1281 { .name = "rx", .dma_req = 22 },
1282 { .name = "tx", .dma_req = 21 },
1283 { .dma_req = -1 }
1284 };
1285
1286 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1287 .name = "mcbsp5",
1288 .class = &omap3xxx_mcbsp_hwmod_class,
1289 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1290 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1291 .main_clk = "mcbsp5_fck",
1292 .prcm = {
1293 .omap2 = {
1294 .prcm_reg_id = 1,
1295 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1296 .module_offs = CORE_MOD,
1297 .idlest_reg_id = 1,
1298 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1299 },
1300 },
1301 .opt_clks = mcbsp15_opt_clks,
1302 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1303 };
1304
1305 /* 'mcbsp sidetone' class */
1306 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1307 .sysc_offs = 0x0010,
1308 .sysc_flags = SYSC_HAS_AUTOIDLE,
1309 .sysc_fields = &omap_hwmod_sysc_type1,
1310 };
1311
1312 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1313 .name = "mcbsp_sidetone",
1314 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1315 };
1316
1317 /* mcbsp2_sidetone */
1318 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1319 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1320 { .irq = -1 },
1321 };
1322
1323 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1324 .name = "mcbsp2_sidetone",
1325 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1326 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1327 .main_clk = "mcbsp2_fck",
1328 .prcm = {
1329 .omap2 = {
1330 .prcm_reg_id = 1,
1331 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1332 .module_offs = OMAP3430_PER_MOD,
1333 .idlest_reg_id = 1,
1334 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1335 },
1336 },
1337 };
1338
1339 /* mcbsp3_sidetone */
1340 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1341 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1342 { .irq = -1 },
1343 };
1344
1345 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1346 .name = "mcbsp3_sidetone",
1347 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1348 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1349 .main_clk = "mcbsp3_fck",
1350 .prcm = {
1351 .omap2 = {
1352 .prcm_reg_id = 1,
1353 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1354 .module_offs = OMAP3430_PER_MOD,
1355 .idlest_reg_id = 1,
1356 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1357 },
1358 },
1359 };
1360
1361 /* SR common */
1362 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1363 .clkact_shift = 20,
1364 };
1365
1366 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1367 .sysc_offs = 0x24,
1368 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1369 .clockact = CLOCKACT_TEST_ICLK,
1370 .sysc_fields = &omap34xx_sr_sysc_fields,
1371 };
1372
1373 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1374 .name = "smartreflex",
1375 .sysc = &omap34xx_sr_sysc,
1376 .rev = 1,
1377 };
1378
1379 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1380 .sidle_shift = 24,
1381 .enwkup_shift = 26,
1382 };
1383
1384 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1385 .sysc_offs = 0x38,
1386 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1387 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1388 SYSC_NO_CACHE),
1389 .sysc_fields = &omap36xx_sr_sysc_fields,
1390 };
1391
1392 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1393 .name = "smartreflex",
1394 .sysc = &omap36xx_sr_sysc,
1395 .rev = 2,
1396 };
1397
1398 /* SR1 */
1399 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1400 .sensor_voltdm_name = "mpu_iva",
1401 };
1402
1403 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1404 { .irq = 18 + OMAP_INTC_START, },
1405 { .irq = -1 },
1406 };
1407
1408 static struct omap_hwmod omap34xx_sr1_hwmod = {
1409 .name = "smartreflex_mpu_iva",
1410 .class = &omap34xx_smartreflex_hwmod_class,
1411 .main_clk = "sr1_fck",
1412 .prcm = {
1413 .omap2 = {
1414 .prcm_reg_id = 1,
1415 .module_bit = OMAP3430_EN_SR1_SHIFT,
1416 .module_offs = WKUP_MOD,
1417 .idlest_reg_id = 1,
1418 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1419 },
1420 },
1421 .dev_attr = &sr1_dev_attr,
1422 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1423 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1424 };
1425
1426 static struct omap_hwmod omap36xx_sr1_hwmod = {
1427 .name = "smartreflex_mpu_iva",
1428 .class = &omap36xx_smartreflex_hwmod_class,
1429 .main_clk = "sr1_fck",
1430 .prcm = {
1431 .omap2 = {
1432 .prcm_reg_id = 1,
1433 .module_bit = OMAP3430_EN_SR1_SHIFT,
1434 .module_offs = WKUP_MOD,
1435 .idlest_reg_id = 1,
1436 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1437 },
1438 },
1439 .dev_attr = &sr1_dev_attr,
1440 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1441 };
1442
1443 /* SR2 */
1444 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1445 .sensor_voltdm_name = "core",
1446 };
1447
1448 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1449 { .irq = 19 + OMAP_INTC_START, },
1450 { .irq = -1 },
1451 };
1452
1453 static struct omap_hwmod omap34xx_sr2_hwmod = {
1454 .name = "smartreflex_core",
1455 .class = &omap34xx_smartreflex_hwmod_class,
1456 .main_clk = "sr2_fck",
1457 .prcm = {
1458 .omap2 = {
1459 .prcm_reg_id = 1,
1460 .module_bit = OMAP3430_EN_SR2_SHIFT,
1461 .module_offs = WKUP_MOD,
1462 .idlest_reg_id = 1,
1463 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1464 },
1465 },
1466 .dev_attr = &sr2_dev_attr,
1467 .mpu_irqs = omap3_smartreflex_core_irqs,
1468 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1469 };
1470
1471 static struct omap_hwmod omap36xx_sr2_hwmod = {
1472 .name = "smartreflex_core",
1473 .class = &omap36xx_smartreflex_hwmod_class,
1474 .main_clk = "sr2_fck",
1475 .prcm = {
1476 .omap2 = {
1477 .prcm_reg_id = 1,
1478 .module_bit = OMAP3430_EN_SR2_SHIFT,
1479 .module_offs = WKUP_MOD,
1480 .idlest_reg_id = 1,
1481 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1482 },
1483 },
1484 .dev_attr = &sr2_dev_attr,
1485 .mpu_irqs = omap3_smartreflex_core_irqs,
1486 };
1487
1488 /*
1489 * 'mailbox' class
1490 * mailbox module allowing communication between the on-chip processors
1491 * using a queued mailbox-interrupt mechanism.
1492 */
1493
1494 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1495 .rev_offs = 0x000,
1496 .sysc_offs = 0x010,
1497 .syss_offs = 0x014,
1498 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1499 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1500 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1501 .sysc_fields = &omap_hwmod_sysc_type1,
1502 };
1503
1504 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1505 .name = "mailbox",
1506 .sysc = &omap3xxx_mailbox_sysc,
1507 };
1508
1509 static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
1510 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
1511 };
1512
1513 static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
1514 .num_users = 2,
1515 .num_fifos = 2,
1516 .info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info),
1517 .info = omap3xxx_mailbox_info,
1518 };
1519
1520 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1521 { .irq = 26 + OMAP_INTC_START, },
1522 { .irq = -1 },
1523 };
1524
1525 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1526 .name = "mailbox",
1527 .class = &omap3xxx_mailbox_hwmod_class,
1528 .mpu_irqs = omap3xxx_mailbox_irqs,
1529 .main_clk = "mailboxes_ick",
1530 .prcm = {
1531 .omap2 = {
1532 .prcm_reg_id = 1,
1533 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1534 .module_offs = CORE_MOD,
1535 .idlest_reg_id = 1,
1536 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1537 },
1538 },
1539 .dev_attr = &omap3xxx_mailbox_attrs,
1540 };
1541
1542 /*
1543 * 'mcspi' class
1544 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1545 * bus
1546 */
1547
1548 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1549 .rev_offs = 0x0000,
1550 .sysc_offs = 0x0010,
1551 .syss_offs = 0x0014,
1552 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1553 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1554 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1556 .sysc_fields = &omap_hwmod_sysc_type1,
1557 };
1558
1559 static struct omap_hwmod_class omap34xx_mcspi_class = {
1560 .name = "mcspi",
1561 .sysc = &omap34xx_mcspi_sysc,
1562 .rev = OMAP3_MCSPI_REV,
1563 };
1564
1565 /* mcspi1 */
1566 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1567 .num_chipselect = 4,
1568 };
1569
1570 static struct omap_hwmod omap34xx_mcspi1 = {
1571 .name = "mcspi1",
1572 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1573 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1574 .main_clk = "mcspi1_fck",
1575 .prcm = {
1576 .omap2 = {
1577 .module_offs = CORE_MOD,
1578 .prcm_reg_id = 1,
1579 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1580 .idlest_reg_id = 1,
1581 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1582 },
1583 },
1584 .class = &omap34xx_mcspi_class,
1585 .dev_attr = &omap_mcspi1_dev_attr,
1586 };
1587
1588 /* mcspi2 */
1589 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1590 .num_chipselect = 2,
1591 };
1592
1593 static struct omap_hwmod omap34xx_mcspi2 = {
1594 .name = "mcspi2",
1595 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1596 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1597 .main_clk = "mcspi2_fck",
1598 .prcm = {
1599 .omap2 = {
1600 .module_offs = CORE_MOD,
1601 .prcm_reg_id = 1,
1602 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1603 .idlest_reg_id = 1,
1604 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1605 },
1606 },
1607 .class = &omap34xx_mcspi_class,
1608 .dev_attr = &omap_mcspi2_dev_attr,
1609 };
1610
1611 /* mcspi3 */
1612 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1613 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1614 { .irq = -1 },
1615 };
1616
1617 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1618 { .name = "tx0", .dma_req = 15 },
1619 { .name = "rx0", .dma_req = 16 },
1620 { .name = "tx1", .dma_req = 23 },
1621 { .name = "rx1", .dma_req = 24 },
1622 { .dma_req = -1 }
1623 };
1624
1625 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1626 .num_chipselect = 2,
1627 };
1628
1629 static struct omap_hwmod omap34xx_mcspi3 = {
1630 .name = "mcspi3",
1631 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1632 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1633 .main_clk = "mcspi3_fck",
1634 .prcm = {
1635 .omap2 = {
1636 .module_offs = CORE_MOD,
1637 .prcm_reg_id = 1,
1638 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1639 .idlest_reg_id = 1,
1640 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1641 },
1642 },
1643 .class = &omap34xx_mcspi_class,
1644 .dev_attr = &omap_mcspi3_dev_attr,
1645 };
1646
1647 /* mcspi4 */
1648 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1649 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1650 { .irq = -1 },
1651 };
1652
1653 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1654 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1655 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1656 { .dma_req = -1 }
1657 };
1658
1659 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1660 .num_chipselect = 1,
1661 };
1662
1663 static struct omap_hwmod omap34xx_mcspi4 = {
1664 .name = "mcspi4",
1665 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1666 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1667 .main_clk = "mcspi4_fck",
1668 .prcm = {
1669 .omap2 = {
1670 .module_offs = CORE_MOD,
1671 .prcm_reg_id = 1,
1672 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1673 .idlest_reg_id = 1,
1674 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1675 },
1676 },
1677 .class = &omap34xx_mcspi_class,
1678 .dev_attr = &omap_mcspi4_dev_attr,
1679 };
1680
1681 /* usbhsotg */
1682 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1683 .rev_offs = 0x0400,
1684 .sysc_offs = 0x0404,
1685 .syss_offs = 0x0408,
1686 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1687 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1688 SYSC_HAS_AUTOIDLE),
1689 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1690 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1691 .sysc_fields = &omap_hwmod_sysc_type1,
1692 };
1693
1694 static struct omap_hwmod_class usbotg_class = {
1695 .name = "usbotg",
1696 .sysc = &omap3xxx_usbhsotg_sysc,
1697 };
1698
1699 /* usb_otg_hs */
1700 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1701
1702 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1703 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1704 { .irq = -1 },
1705 };
1706
1707 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1708 .name = "usb_otg_hs",
1709 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1710 .main_clk = "hsotgusb_ick",
1711 .prcm = {
1712 .omap2 = {
1713 .prcm_reg_id = 1,
1714 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1715 .module_offs = CORE_MOD,
1716 .idlest_reg_id = 1,
1717 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1718 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1719 },
1720 },
1721 .class = &usbotg_class,
1722
1723 /*
1724 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1725 * broken when autoidle is enabled
1726 * workaround is to disable the autoidle bit at module level.
1727 *
1728 * Enabling the device in any other MIDLEMODE setting but force-idle
1729 * causes core_pwrdm not enter idle states at least on OMAP3630.
1730 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1731 * signal when MIDLEMODE is set to force-idle.
1732 */
1733 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1734 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1735 };
1736
1737 /* usb_otg_hs */
1738 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1739 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1740 { .irq = -1 },
1741 };
1742
1743 static struct omap_hwmod_class am35xx_usbotg_class = {
1744 .name = "am35xx_usbotg",
1745 };
1746
1747 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1748 .name = "am35x_otg_hs",
1749 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1750 .main_clk = "hsotgusb_fck",
1751 .class = &am35xx_usbotg_class,
1752 .flags = HWMOD_NO_IDLEST,
1753 };
1754
1755 /* MMC/SD/SDIO common */
1756 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1757 .rev_offs = 0x1fc,
1758 .sysc_offs = 0x10,
1759 .syss_offs = 0x14,
1760 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1761 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1762 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1763 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1764 .sysc_fields = &omap_hwmod_sysc_type1,
1765 };
1766
1767 static struct omap_hwmod_class omap34xx_mmc_class = {
1768 .name = "mmc",
1769 .sysc = &omap34xx_mmc_sysc,
1770 };
1771
1772 /* MMC/SD/SDIO1 */
1773
1774 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1775 { .irq = 83 + OMAP_INTC_START, },
1776 { .irq = -1 },
1777 };
1778
1779 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1780 { .name = "tx", .dma_req = 61, },
1781 { .name = "rx", .dma_req = 62, },
1782 { .dma_req = -1 }
1783 };
1784
1785 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1786 { .role = "dbck", .clk = "omap_32k_fck", },
1787 };
1788
1789 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1790 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1791 };
1792
1793 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1794 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1795 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1796 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1797 };
1798
1799 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1800 .name = "mmc1",
1801 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1802 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1803 .opt_clks = omap34xx_mmc1_opt_clks,
1804 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1805 .main_clk = "mmchs1_fck",
1806 .prcm = {
1807 .omap2 = {
1808 .module_offs = CORE_MOD,
1809 .prcm_reg_id = 1,
1810 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1811 .idlest_reg_id = 1,
1812 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1813 },
1814 },
1815 .dev_attr = &mmc1_pre_es3_dev_attr,
1816 .class = &omap34xx_mmc_class,
1817 };
1818
1819 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1820 .name = "mmc1",
1821 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1822 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1823 .opt_clks = omap34xx_mmc1_opt_clks,
1824 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1825 .main_clk = "mmchs1_fck",
1826 .prcm = {
1827 .omap2 = {
1828 .module_offs = CORE_MOD,
1829 .prcm_reg_id = 1,
1830 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1831 .idlest_reg_id = 1,
1832 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1833 },
1834 },
1835 .dev_attr = &mmc1_dev_attr,
1836 .class = &omap34xx_mmc_class,
1837 };
1838
1839 /* MMC/SD/SDIO2 */
1840
1841 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1842 { .irq = 86 + OMAP_INTC_START, },
1843 { .irq = -1 },
1844 };
1845
1846 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1847 { .name = "tx", .dma_req = 47, },
1848 { .name = "rx", .dma_req = 48, },
1849 { .dma_req = -1 }
1850 };
1851
1852 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1853 { .role = "dbck", .clk = "omap_32k_fck", },
1854 };
1855
1856 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1857 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1858 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1859 };
1860
1861 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1862 .name = "mmc2",
1863 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1864 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1865 .opt_clks = omap34xx_mmc2_opt_clks,
1866 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1867 .main_clk = "mmchs2_fck",
1868 .prcm = {
1869 .omap2 = {
1870 .module_offs = CORE_MOD,
1871 .prcm_reg_id = 1,
1872 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1873 .idlest_reg_id = 1,
1874 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1875 },
1876 },
1877 .dev_attr = &mmc2_pre_es3_dev_attr,
1878 .class = &omap34xx_mmc_class,
1879 };
1880
1881 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1882 .name = "mmc2",
1883 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1884 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1885 .opt_clks = omap34xx_mmc2_opt_clks,
1886 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1887 .main_clk = "mmchs2_fck",
1888 .prcm = {
1889 .omap2 = {
1890 .module_offs = CORE_MOD,
1891 .prcm_reg_id = 1,
1892 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1893 .idlest_reg_id = 1,
1894 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1895 },
1896 },
1897 .class = &omap34xx_mmc_class,
1898 };
1899
1900 /* MMC/SD/SDIO3 */
1901
1902 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1903 { .irq = 94 + OMAP_INTC_START, },
1904 { .irq = -1 },
1905 };
1906
1907 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1908 { .name = "tx", .dma_req = 77, },
1909 { .name = "rx", .dma_req = 78, },
1910 { .dma_req = -1 }
1911 };
1912
1913 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1914 { .role = "dbck", .clk = "omap_32k_fck", },
1915 };
1916
1917 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1918 .name = "mmc3",
1919 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1920 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1921 .opt_clks = omap34xx_mmc3_opt_clks,
1922 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1923 .main_clk = "mmchs3_fck",
1924 .prcm = {
1925 .omap2 = {
1926 .prcm_reg_id = 1,
1927 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1928 .idlest_reg_id = 1,
1929 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1930 },
1931 },
1932 .class = &omap34xx_mmc_class,
1933 };
1934
1935 /*
1936 * 'usb_host_hs' class
1937 * high-speed multi-port usb host controller
1938 */
1939
1940 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1941 .rev_offs = 0x0000,
1942 .sysc_offs = 0x0010,
1943 .syss_offs = 0x0014,
1944 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1945 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1946 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1947 SYSS_HAS_RESET_STATUS),
1948 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1949 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1950 .sysc_fields = &omap_hwmod_sysc_type1,
1951 };
1952
1953 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1954 .name = "usb_host_hs",
1955 .sysc = &omap3xxx_usb_host_hs_sysc,
1956 };
1957
1958 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1959 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1960 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1961 { .irq = -1 },
1962 };
1963
1964 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1965 .name = "usb_host_hs",
1966 .class = &omap3xxx_usb_host_hs_hwmod_class,
1967 .clkdm_name = "usbhost_clkdm",
1968 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1969 .main_clk = "usbhost_48m_fck",
1970 .prcm = {
1971 .omap2 = {
1972 .module_offs = OMAP3430ES2_USBHOST_MOD,
1973 .prcm_reg_id = 1,
1974 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1975 .idlest_reg_id = 1,
1976 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1977 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1978 },
1979 },
1980
1981 /*
1982 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1983 * id: i660
1984 *
1985 * Description:
1986 * In the following configuration :
1987 * - USBHOST module is set to smart-idle mode
1988 * - PRCM asserts idle_req to the USBHOST module ( This typically
1989 * happens when the system is going to a low power mode : all ports
1990 * have been suspended, the master part of the USBHOST module has
1991 * entered the standby state, and SW has cut the functional clocks)
1992 * - an USBHOST interrupt occurs before the module is able to answer
1993 * idle_ack, typically a remote wakeup IRQ.
1994 * Then the USB HOST module will enter a deadlock situation where it
1995 * is no more accessible nor functional.
1996 *
1997 * Workaround:
1998 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1999 */
2000
2001 /*
2002 * Errata: USB host EHCI may stall when entering smart-standby mode
2003 * Id: i571
2004 *
2005 * Description:
2006 * When the USBHOST module is set to smart-standby mode, and when it is
2007 * ready to enter the standby state (i.e. all ports are suspended and
2008 * all attached devices are in suspend mode), then it can wrongly assert
2009 * the Mstandby signal too early while there are still some residual OCP
2010 * transactions ongoing. If this condition occurs, the internal state
2011 * machine may go to an undefined state and the USB link may be stuck
2012 * upon the next resume.
2013 *
2014 * Workaround:
2015 * Don't use smart standby; use only force standby,
2016 * hence HWMOD_SWSUP_MSTANDBY
2017 */
2018
2019 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2020 };
2021
2022 /*
2023 * 'usb_tll_hs' class
2024 * usb_tll_hs module is the adapter on the usb_host_hs ports
2025 */
2026 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2027 .rev_offs = 0x0000,
2028 .sysc_offs = 0x0010,
2029 .syss_offs = 0x0014,
2030 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2032 SYSC_HAS_AUTOIDLE),
2033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2034 .sysc_fields = &omap_hwmod_sysc_type1,
2035 };
2036
2037 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2038 .name = "usb_tll_hs",
2039 .sysc = &omap3xxx_usb_tll_hs_sysc,
2040 };
2041
2042 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2043 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2044 { .irq = -1 },
2045 };
2046
2047 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2048 .name = "usb_tll_hs",
2049 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2050 .clkdm_name = "core_l4_clkdm",
2051 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2052 .main_clk = "usbtll_fck",
2053 .prcm = {
2054 .omap2 = {
2055 .module_offs = CORE_MOD,
2056 .prcm_reg_id = 3,
2057 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2058 .idlest_reg_id = 3,
2059 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2060 },
2061 },
2062 };
2063
2064 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2065 .name = "hdq1w",
2066 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2067 .main_clk = "hdq_fck",
2068 .prcm = {
2069 .omap2 = {
2070 .module_offs = CORE_MOD,
2071 .prcm_reg_id = 1,
2072 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2073 .idlest_reg_id = 1,
2074 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2075 },
2076 },
2077 .class = &omap2_hdq1w_class,
2078 };
2079
2080 /* SAD2D */
2081 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2082 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2083 { .name = "rst_modem_sw", .rst_shift = 1 },
2084 };
2085
2086 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2087 .name = "sad2d",
2088 };
2089
2090 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2091 .name = "sad2d",
2092 .rst_lines = omap3xxx_sad2d_resets,
2093 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2094 .main_clk = "sad2d_ick",
2095 .prcm = {
2096 .omap2 = {
2097 .module_offs = CORE_MOD,
2098 .prcm_reg_id = 1,
2099 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2100 .idlest_reg_id = 1,
2101 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2102 },
2103 },
2104 .class = &omap3xxx_sad2d_class,
2105 };
2106
2107 /*
2108 * '32K sync counter' class
2109 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2110 */
2111 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2112 .rev_offs = 0x0000,
2113 .sysc_offs = 0x0004,
2114 .sysc_flags = SYSC_HAS_SIDLEMODE,
2115 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2116 .sysc_fields = &omap_hwmod_sysc_type1,
2117 };
2118
2119 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2120 .name = "counter",
2121 .sysc = &omap3xxx_counter_sysc,
2122 };
2123
2124 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2125 .name = "counter_32k",
2126 .class = &omap3xxx_counter_hwmod_class,
2127 .clkdm_name = "wkup_clkdm",
2128 .flags = HWMOD_SWSUP_SIDLE,
2129 .main_clk = "wkup_32k_fck",
2130 .prcm = {
2131 .omap2 = {
2132 .module_offs = WKUP_MOD,
2133 .prcm_reg_id = 1,
2134 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2135 .idlest_reg_id = 1,
2136 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2137 },
2138 },
2139 };
2140
2141 /*
2142 * 'gpmc' class
2143 * general purpose memory controller
2144 */
2145
2146 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2147 .rev_offs = 0x0000,
2148 .sysc_offs = 0x0010,
2149 .syss_offs = 0x0014,
2150 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2151 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2152 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2153 .sysc_fields = &omap_hwmod_sysc_type1,
2154 };
2155
2156 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2157 .name = "gpmc",
2158 .sysc = &omap3xxx_gpmc_sysc,
2159 };
2160
2161 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2162 { .irq = 20 + OMAP_INTC_START, },
2163 { .irq = -1 }
2164 };
2165
2166 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2167 .name = "gpmc",
2168 .class = &omap3xxx_gpmc_hwmod_class,
2169 .clkdm_name = "core_l3_clkdm",
2170 .mpu_irqs = omap3xxx_gpmc_irqs,
2171 .main_clk = "gpmc_fck",
2172 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2173 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
2174 };
2175
2176 /*
2177 * interfaces
2178 */
2179
2180 /* L3 -> L4_CORE interface */
2181 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2182 .master = &omap3xxx_l3_main_hwmod,
2183 .slave = &omap3xxx_l4_core_hwmod,
2184 .user = OCP_USER_MPU | OCP_USER_SDMA,
2185 };
2186
2187 /* L3 -> L4_PER interface */
2188 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2189 .master = &omap3xxx_l3_main_hwmod,
2190 .slave = &omap3xxx_l4_per_hwmod,
2191 .user = OCP_USER_MPU | OCP_USER_SDMA,
2192 };
2193
2194 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2195 {
2196 .pa_start = 0x68000000,
2197 .pa_end = 0x6800ffff,
2198 .flags = ADDR_TYPE_RT,
2199 },
2200 { }
2201 };
2202
2203 /* MPU -> L3 interface */
2204 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2205 .master = &omap3xxx_mpu_hwmod,
2206 .slave = &omap3xxx_l3_main_hwmod,
2207 .addr = omap3xxx_l3_main_addrs,
2208 .user = OCP_USER_MPU,
2209 };
2210
2211 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2212 {
2213 .pa_start = 0x54000000,
2214 .pa_end = 0x547fffff,
2215 .flags = ADDR_TYPE_RT,
2216 },
2217 { }
2218 };
2219
2220 /* l3 -> debugss */
2221 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2222 .master = &omap3xxx_l3_main_hwmod,
2223 .slave = &omap3xxx_debugss_hwmod,
2224 .addr = omap3xxx_l4_emu_addrs,
2225 .user = OCP_USER_MPU,
2226 };
2227
2228 /* DSS -> l3 */
2229 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2230 .master = &omap3430es1_dss_core_hwmod,
2231 .slave = &omap3xxx_l3_main_hwmod,
2232 .user = OCP_USER_MPU | OCP_USER_SDMA,
2233 };
2234
2235 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2236 .master = &omap3xxx_dss_core_hwmod,
2237 .slave = &omap3xxx_l3_main_hwmod,
2238 .fw = {
2239 .omap2 = {
2240 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2241 .flags = OMAP_FIREWALL_L3,
2242 }
2243 },
2244 .user = OCP_USER_MPU | OCP_USER_SDMA,
2245 };
2246
2247 /* l3_core -> usbhsotg interface */
2248 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2249 .master = &omap3xxx_usbhsotg_hwmod,
2250 .slave = &omap3xxx_l3_main_hwmod,
2251 .clk = "core_l3_ick",
2252 .user = OCP_USER_MPU,
2253 };
2254
2255 /* l3_core -> am35xx_usbhsotg interface */
2256 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2257 .master = &am35xx_usbhsotg_hwmod,
2258 .slave = &omap3xxx_l3_main_hwmod,
2259 .clk = "hsotgusb_ick",
2260 .user = OCP_USER_MPU,
2261 };
2262
2263 /* l3_core -> sad2d interface */
2264 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2265 .master = &omap3xxx_sad2d_hwmod,
2266 .slave = &omap3xxx_l3_main_hwmod,
2267 .clk = "core_l3_ick",
2268 .user = OCP_USER_MPU,
2269 };
2270
2271 /* L4_CORE -> L4_WKUP interface */
2272 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap3xxx_l4_wkup_hwmod,
2275 .user = OCP_USER_MPU | OCP_USER_SDMA,
2276 };
2277
2278 /* L4 CORE -> MMC1 interface */
2279 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2280 .master = &omap3xxx_l4_core_hwmod,
2281 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2282 .clk = "mmchs1_ick",
2283 .addr = omap2430_mmc1_addr_space,
2284 .user = OCP_USER_MPU | OCP_USER_SDMA,
2285 .flags = OMAP_FIREWALL_L4
2286 };
2287
2288 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2289 .master = &omap3xxx_l4_core_hwmod,
2290 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2291 .clk = "mmchs1_ick",
2292 .addr = omap2430_mmc1_addr_space,
2293 .user = OCP_USER_MPU | OCP_USER_SDMA,
2294 .flags = OMAP_FIREWALL_L4
2295 };
2296
2297 /* L4 CORE -> MMC2 interface */
2298 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2299 .master = &omap3xxx_l4_core_hwmod,
2300 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2301 .clk = "mmchs2_ick",
2302 .addr = omap2430_mmc2_addr_space,
2303 .user = OCP_USER_MPU | OCP_USER_SDMA,
2304 .flags = OMAP_FIREWALL_L4
2305 };
2306
2307 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2308 .master = &omap3xxx_l4_core_hwmod,
2309 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2310 .clk = "mmchs2_ick",
2311 .addr = omap2430_mmc2_addr_space,
2312 .user = OCP_USER_MPU | OCP_USER_SDMA,
2313 .flags = OMAP_FIREWALL_L4
2314 };
2315
2316 /* L4 CORE -> MMC3 interface */
2317 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2318 {
2319 .pa_start = 0x480ad000,
2320 .pa_end = 0x480ad1ff,
2321 .flags = ADDR_TYPE_RT,
2322 },
2323 { }
2324 };
2325
2326 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2327 .master = &omap3xxx_l4_core_hwmod,
2328 .slave = &omap3xxx_mmc3_hwmod,
2329 .clk = "mmchs3_ick",
2330 .addr = omap3xxx_mmc3_addr_space,
2331 .user = OCP_USER_MPU | OCP_USER_SDMA,
2332 .flags = OMAP_FIREWALL_L4
2333 };
2334
2335 /* L4 CORE -> UART1 interface */
2336 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2337 {
2338 .pa_start = OMAP3_UART1_BASE,
2339 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2340 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2341 },
2342 { }
2343 };
2344
2345 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2346 .master = &omap3xxx_l4_core_hwmod,
2347 .slave = &omap3xxx_uart1_hwmod,
2348 .clk = "uart1_ick",
2349 .addr = omap3xxx_uart1_addr_space,
2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2351 };
2352
2353 /* L4 CORE -> UART2 interface */
2354 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2355 {
2356 .pa_start = OMAP3_UART2_BASE,
2357 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2358 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2359 },
2360 { }
2361 };
2362
2363 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2364 .master = &omap3xxx_l4_core_hwmod,
2365 .slave = &omap3xxx_uart2_hwmod,
2366 .clk = "uart2_ick",
2367 .addr = omap3xxx_uart2_addr_space,
2368 .user = OCP_USER_MPU | OCP_USER_SDMA,
2369 };
2370
2371 /* L4 PER -> UART3 interface */
2372 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2373 {
2374 .pa_start = OMAP3_UART3_BASE,
2375 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2376 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2377 },
2378 { }
2379 };
2380
2381 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2382 .master = &omap3xxx_l4_per_hwmod,
2383 .slave = &omap3xxx_uart3_hwmod,
2384 .clk = "uart3_ick",
2385 .addr = omap3xxx_uart3_addr_space,
2386 .user = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388
2389 /* L4 PER -> UART4 interface */
2390 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2391 {
2392 .pa_start = OMAP3_UART4_BASE,
2393 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2394 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2395 },
2396 { }
2397 };
2398
2399 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2400 .master = &omap3xxx_l4_per_hwmod,
2401 .slave = &omap36xx_uart4_hwmod,
2402 .clk = "uart4_ick",
2403 .addr = omap36xx_uart4_addr_space,
2404 .user = OCP_USER_MPU | OCP_USER_SDMA,
2405 };
2406
2407 /* AM35xx: L4 CORE -> UART4 interface */
2408 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2409 {
2410 .pa_start = OMAP3_UART4_AM35XX_BASE,
2411 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2412 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2413 },
2414 { }
2415 };
2416
2417 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2418 .master = &omap3xxx_l4_core_hwmod,
2419 .slave = &am35xx_uart4_hwmod,
2420 .clk = "uart4_ick",
2421 .addr = am35xx_uart4_addr_space,
2422 .user = OCP_USER_MPU | OCP_USER_SDMA,
2423 };
2424
2425 /* L4 CORE -> I2C1 interface */
2426 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2427 .master = &omap3xxx_l4_core_hwmod,
2428 .slave = &omap3xxx_i2c1_hwmod,
2429 .clk = "i2c1_ick",
2430 .addr = omap2_i2c1_addr_space,
2431 .fw = {
2432 .omap2 = {
2433 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2434 .l4_prot_group = 7,
2435 .flags = OMAP_FIREWALL_L4,
2436 }
2437 },
2438 .user = OCP_USER_MPU | OCP_USER_SDMA,
2439 };
2440
2441 /* L4 CORE -> I2C2 interface */
2442 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2443 .master = &omap3xxx_l4_core_hwmod,
2444 .slave = &omap3xxx_i2c2_hwmod,
2445 .clk = "i2c2_ick",
2446 .addr = omap2_i2c2_addr_space,
2447 .fw = {
2448 .omap2 = {
2449 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2450 .l4_prot_group = 7,
2451 .flags = OMAP_FIREWALL_L4,
2452 }
2453 },
2454 .user = OCP_USER_MPU | OCP_USER_SDMA,
2455 };
2456
2457 /* L4 CORE -> I2C3 interface */
2458 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2459 {
2460 .pa_start = 0x48060000,
2461 .pa_end = 0x48060000 + SZ_128 - 1,
2462 .flags = ADDR_TYPE_RT,
2463 },
2464 { }
2465 };
2466
2467 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2468 .master = &omap3xxx_l4_core_hwmod,
2469 .slave = &omap3xxx_i2c3_hwmod,
2470 .clk = "i2c3_ick",
2471 .addr = omap3xxx_i2c3_addr_space,
2472 .fw = {
2473 .omap2 = {
2474 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2475 .l4_prot_group = 7,
2476 .flags = OMAP_FIREWALL_L4,
2477 }
2478 },
2479 .user = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 /* L4 CORE -> SR1 interface */
2483 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2484 {
2485 .pa_start = OMAP34XX_SR1_BASE,
2486 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2487 .flags = ADDR_TYPE_RT,
2488 },
2489 { }
2490 };
2491
2492 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2493 .master = &omap3xxx_l4_core_hwmod,
2494 .slave = &omap34xx_sr1_hwmod,
2495 .clk = "sr_l4_ick",
2496 .addr = omap3_sr1_addr_space,
2497 .user = OCP_USER_MPU,
2498 };
2499
2500 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2501 .master = &omap3xxx_l4_core_hwmod,
2502 .slave = &omap36xx_sr1_hwmod,
2503 .clk = "sr_l4_ick",
2504 .addr = omap3_sr1_addr_space,
2505 .user = OCP_USER_MPU,
2506 };
2507
2508 /* L4 CORE -> SR1 interface */
2509 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2510 {
2511 .pa_start = OMAP34XX_SR2_BASE,
2512 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2513 .flags = ADDR_TYPE_RT,
2514 },
2515 { }
2516 };
2517
2518 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2519 .master = &omap3xxx_l4_core_hwmod,
2520 .slave = &omap34xx_sr2_hwmod,
2521 .clk = "sr_l4_ick",
2522 .addr = omap3_sr2_addr_space,
2523 .user = OCP_USER_MPU,
2524 };
2525
2526 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2527 .master = &omap3xxx_l4_core_hwmod,
2528 .slave = &omap36xx_sr2_hwmod,
2529 .clk = "sr_l4_ick",
2530 .addr = omap3_sr2_addr_space,
2531 .user = OCP_USER_MPU,
2532 };
2533
2534 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2535 {
2536 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2537 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2538 .flags = ADDR_TYPE_RT
2539 },
2540 { }
2541 };
2542
2543 /* l4_core -> usbhsotg */
2544 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2545 .master = &omap3xxx_l4_core_hwmod,
2546 .slave = &omap3xxx_usbhsotg_hwmod,
2547 .clk = "l4_ick",
2548 .addr = omap3xxx_usbhsotg_addrs,
2549 .user = OCP_USER_MPU,
2550 };
2551
2552 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2553 {
2554 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2555 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2556 .flags = ADDR_TYPE_RT
2557 },
2558 { }
2559 };
2560
2561 /* l4_core -> usbhsotg */
2562 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2563 .master = &omap3xxx_l4_core_hwmod,
2564 .slave = &am35xx_usbhsotg_hwmod,
2565 .clk = "hsotgusb_ick",
2566 .addr = am35xx_usbhsotg_addrs,
2567 .user = OCP_USER_MPU,
2568 };
2569
2570 /* L4_WKUP -> L4_SEC interface */
2571 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2572 .master = &omap3xxx_l4_wkup_hwmod,
2573 .slave = &omap3xxx_l4_sec_hwmod,
2574 .user = OCP_USER_MPU | OCP_USER_SDMA,
2575 };
2576
2577 /* IVA2 <- L3 interface */
2578 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2579 .master = &omap3xxx_l3_main_hwmod,
2580 .slave = &omap3xxx_iva_hwmod,
2581 .clk = "core_l3_ick",
2582 .user = OCP_USER_MPU | OCP_USER_SDMA,
2583 };
2584
2585 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2586 {
2587 .pa_start = 0x48318000,
2588 .pa_end = 0x48318000 + SZ_1K - 1,
2589 .flags = ADDR_TYPE_RT
2590 },
2591 { }
2592 };
2593
2594 /* l4_wkup -> timer1 */
2595 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2596 .master = &omap3xxx_l4_wkup_hwmod,
2597 .slave = &omap3xxx_timer1_hwmod,
2598 .clk = "gpt1_ick",
2599 .addr = omap3xxx_timer1_addrs,
2600 .user = OCP_USER_MPU | OCP_USER_SDMA,
2601 };
2602
2603 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2604 {
2605 .pa_start = 0x49032000,
2606 .pa_end = 0x49032000 + SZ_1K - 1,
2607 .flags = ADDR_TYPE_RT
2608 },
2609 { }
2610 };
2611
2612 /* l4_per -> timer2 */
2613 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2614 .master = &omap3xxx_l4_per_hwmod,
2615 .slave = &omap3xxx_timer2_hwmod,
2616 .clk = "gpt2_ick",
2617 .addr = omap3xxx_timer2_addrs,
2618 .user = OCP_USER_MPU | OCP_USER_SDMA,
2619 };
2620
2621 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2622 {
2623 .pa_start = 0x49034000,
2624 .pa_end = 0x49034000 + SZ_1K - 1,
2625 .flags = ADDR_TYPE_RT
2626 },
2627 { }
2628 };
2629
2630 /* l4_per -> timer3 */
2631 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2632 .master = &omap3xxx_l4_per_hwmod,
2633 .slave = &omap3xxx_timer3_hwmod,
2634 .clk = "gpt3_ick",
2635 .addr = omap3xxx_timer3_addrs,
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2640 {
2641 .pa_start = 0x49036000,
2642 .pa_end = 0x49036000 + SZ_1K - 1,
2643 .flags = ADDR_TYPE_RT
2644 },
2645 { }
2646 };
2647
2648 /* l4_per -> timer4 */
2649 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2650 .master = &omap3xxx_l4_per_hwmod,
2651 .slave = &omap3xxx_timer4_hwmod,
2652 .clk = "gpt4_ick",
2653 .addr = omap3xxx_timer4_addrs,
2654 .user = OCP_USER_MPU | OCP_USER_SDMA,
2655 };
2656
2657 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2658 {
2659 .pa_start = 0x49038000,
2660 .pa_end = 0x49038000 + SZ_1K - 1,
2661 .flags = ADDR_TYPE_RT
2662 },
2663 { }
2664 };
2665
2666 /* l4_per -> timer5 */
2667 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2668 .master = &omap3xxx_l4_per_hwmod,
2669 .slave = &omap3xxx_timer5_hwmod,
2670 .clk = "gpt5_ick",
2671 .addr = omap3xxx_timer5_addrs,
2672 .user = OCP_USER_MPU | OCP_USER_SDMA,
2673 };
2674
2675 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2676 {
2677 .pa_start = 0x4903A000,
2678 .pa_end = 0x4903A000 + SZ_1K - 1,
2679 .flags = ADDR_TYPE_RT
2680 },
2681 { }
2682 };
2683
2684 /* l4_per -> timer6 */
2685 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2686 .master = &omap3xxx_l4_per_hwmod,
2687 .slave = &omap3xxx_timer6_hwmod,
2688 .clk = "gpt6_ick",
2689 .addr = omap3xxx_timer6_addrs,
2690 .user = OCP_USER_MPU | OCP_USER_SDMA,
2691 };
2692
2693 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2694 {
2695 .pa_start = 0x4903C000,
2696 .pa_end = 0x4903C000 + SZ_1K - 1,
2697 .flags = ADDR_TYPE_RT
2698 },
2699 { }
2700 };
2701
2702 /* l4_per -> timer7 */
2703 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2704 .master = &omap3xxx_l4_per_hwmod,
2705 .slave = &omap3xxx_timer7_hwmod,
2706 .clk = "gpt7_ick",
2707 .addr = omap3xxx_timer7_addrs,
2708 .user = OCP_USER_MPU | OCP_USER_SDMA,
2709 };
2710
2711 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2712 {
2713 .pa_start = 0x4903E000,
2714 .pa_end = 0x4903E000 + SZ_1K - 1,
2715 .flags = ADDR_TYPE_RT
2716 },
2717 { }
2718 };
2719
2720 /* l4_per -> timer8 */
2721 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2722 .master = &omap3xxx_l4_per_hwmod,
2723 .slave = &omap3xxx_timer8_hwmod,
2724 .clk = "gpt8_ick",
2725 .addr = omap3xxx_timer8_addrs,
2726 .user = OCP_USER_MPU | OCP_USER_SDMA,
2727 };
2728
2729 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2730 {
2731 .pa_start = 0x49040000,
2732 .pa_end = 0x49040000 + SZ_1K - 1,
2733 .flags = ADDR_TYPE_RT
2734 },
2735 { }
2736 };
2737
2738 /* l4_per -> timer9 */
2739 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2740 .master = &omap3xxx_l4_per_hwmod,
2741 .slave = &omap3xxx_timer9_hwmod,
2742 .clk = "gpt9_ick",
2743 .addr = omap3xxx_timer9_addrs,
2744 .user = OCP_USER_MPU | OCP_USER_SDMA,
2745 };
2746
2747 /* l4_core -> timer10 */
2748 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2749 .master = &omap3xxx_l4_core_hwmod,
2750 .slave = &omap3xxx_timer10_hwmod,
2751 .clk = "gpt10_ick",
2752 .addr = omap2_timer10_addrs,
2753 .user = OCP_USER_MPU | OCP_USER_SDMA,
2754 };
2755
2756 /* l4_core -> timer11 */
2757 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2758 .master = &omap3xxx_l4_core_hwmod,
2759 .slave = &omap3xxx_timer11_hwmod,
2760 .clk = "gpt11_ick",
2761 .addr = omap2_timer11_addrs,
2762 .user = OCP_USER_MPU | OCP_USER_SDMA,
2763 };
2764
2765 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2766 {
2767 .pa_start = 0x48304000,
2768 .pa_end = 0x48304000 + SZ_1K - 1,
2769 .flags = ADDR_TYPE_RT
2770 },
2771 { }
2772 };
2773
2774 /* l4_core -> timer12 */
2775 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2776 .master = &omap3xxx_l4_sec_hwmod,
2777 .slave = &omap3xxx_timer12_hwmod,
2778 .clk = "gpt12_ick",
2779 .addr = omap3xxx_timer12_addrs,
2780 .user = OCP_USER_MPU | OCP_USER_SDMA,
2781 };
2782
2783 /* l4_wkup -> wd_timer2 */
2784 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2785 {
2786 .pa_start = 0x48314000,
2787 .pa_end = 0x4831407f,
2788 .flags = ADDR_TYPE_RT
2789 },
2790 { }
2791 };
2792
2793 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2794 .master = &omap3xxx_l4_wkup_hwmod,
2795 .slave = &omap3xxx_wd_timer2_hwmod,
2796 .clk = "wdt2_ick",
2797 .addr = omap3xxx_wd_timer2_addrs,
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799 };
2800
2801 /* l4_core -> dss */
2802 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2803 .master = &omap3xxx_l4_core_hwmod,
2804 .slave = &omap3430es1_dss_core_hwmod,
2805 .clk = "dss_ick",
2806 .addr = omap2_dss_addrs,
2807 .fw = {
2808 .omap2 = {
2809 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2810 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2811 .flags = OMAP_FIREWALL_L4,
2812 }
2813 },
2814 .user = OCP_USER_MPU | OCP_USER_SDMA,
2815 };
2816
2817 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2818 .master = &omap3xxx_l4_core_hwmod,
2819 .slave = &omap3xxx_dss_core_hwmod,
2820 .clk = "dss_ick",
2821 .addr = omap2_dss_addrs,
2822 .fw = {
2823 .omap2 = {
2824 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2825 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2826 .flags = OMAP_FIREWALL_L4,
2827 }
2828 },
2829 .user = OCP_USER_MPU | OCP_USER_SDMA,
2830 };
2831
2832 /* l4_core -> dss_dispc */
2833 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2834 .master = &omap3xxx_l4_core_hwmod,
2835 .slave = &omap3xxx_dss_dispc_hwmod,
2836 .clk = "dss_ick",
2837 .addr = omap2_dss_dispc_addrs,
2838 .fw = {
2839 .omap2 = {
2840 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2841 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2842 .flags = OMAP_FIREWALL_L4,
2843 }
2844 },
2845 .user = OCP_USER_MPU | OCP_USER_SDMA,
2846 };
2847
2848 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2849 {
2850 .pa_start = 0x4804FC00,
2851 .pa_end = 0x4804FFFF,
2852 .flags = ADDR_TYPE_RT
2853 },
2854 { }
2855 };
2856
2857 /* l4_core -> dss_dsi1 */
2858 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2859 .master = &omap3xxx_l4_core_hwmod,
2860 .slave = &omap3xxx_dss_dsi1_hwmod,
2861 .clk = "dss_ick",
2862 .addr = omap3xxx_dss_dsi1_addrs,
2863 .fw = {
2864 .omap2 = {
2865 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2866 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2867 .flags = OMAP_FIREWALL_L4,
2868 }
2869 },
2870 .user = OCP_USER_MPU | OCP_USER_SDMA,
2871 };
2872
2873 /* l4_core -> dss_rfbi */
2874 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2875 .master = &omap3xxx_l4_core_hwmod,
2876 .slave = &omap3xxx_dss_rfbi_hwmod,
2877 .clk = "dss_ick",
2878 .addr = omap2_dss_rfbi_addrs,
2879 .fw = {
2880 .omap2 = {
2881 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2882 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2883 .flags = OMAP_FIREWALL_L4,
2884 }
2885 },
2886 .user = OCP_USER_MPU | OCP_USER_SDMA,
2887 };
2888
2889 /* l4_core -> dss_venc */
2890 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2891 .master = &omap3xxx_l4_core_hwmod,
2892 .slave = &omap3xxx_dss_venc_hwmod,
2893 .clk = "dss_ick",
2894 .addr = omap2_dss_venc_addrs,
2895 .fw = {
2896 .omap2 = {
2897 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2898 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2899 .flags = OMAP_FIREWALL_L4,
2900 }
2901 },
2902 .flags = OCPIF_SWSUP_IDLE,
2903 .user = OCP_USER_MPU | OCP_USER_SDMA,
2904 };
2905
2906 /* l4_wkup -> gpio1 */
2907 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2908 {
2909 .pa_start = 0x48310000,
2910 .pa_end = 0x483101ff,
2911 .flags = ADDR_TYPE_RT
2912 },
2913 { }
2914 };
2915
2916 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2917 .master = &omap3xxx_l4_wkup_hwmod,
2918 .slave = &omap3xxx_gpio1_hwmod,
2919 .addr = omap3xxx_gpio1_addrs,
2920 .user = OCP_USER_MPU | OCP_USER_SDMA,
2921 };
2922
2923 /* l4_per -> gpio2 */
2924 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2925 {
2926 .pa_start = 0x49050000,
2927 .pa_end = 0x490501ff,
2928 .flags = ADDR_TYPE_RT
2929 },
2930 { }
2931 };
2932
2933 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2934 .master = &omap3xxx_l4_per_hwmod,
2935 .slave = &omap3xxx_gpio2_hwmod,
2936 .addr = omap3xxx_gpio2_addrs,
2937 .user = OCP_USER_MPU | OCP_USER_SDMA,
2938 };
2939
2940 /* l4_per -> gpio3 */
2941 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2942 {
2943 .pa_start = 0x49052000,
2944 .pa_end = 0x490521ff,
2945 .flags = ADDR_TYPE_RT
2946 },
2947 { }
2948 };
2949
2950 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2951 .master = &omap3xxx_l4_per_hwmod,
2952 .slave = &omap3xxx_gpio3_hwmod,
2953 .addr = omap3xxx_gpio3_addrs,
2954 .user = OCP_USER_MPU | OCP_USER_SDMA,
2955 };
2956
2957 /*
2958 * 'mmu' class
2959 * The memory management unit performs virtual to physical address translation
2960 * for its requestors.
2961 */
2962
2963 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2964 .rev_offs = 0x000,
2965 .sysc_offs = 0x010,
2966 .syss_offs = 0x014,
2967 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2968 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2969 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2970 .sysc_fields = &omap_hwmod_sysc_type1,
2971 };
2972
2973 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2974 .name = "mmu",
2975 .sysc = &mmu_sysc,
2976 };
2977
2978 /* mmu isp */
2979
2980 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2981 .nr_tlb_entries = 8,
2982 };
2983
2984 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2985 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2986 { .irq = 24 + OMAP_INTC_START, },
2987 { .irq = -1 }
2988 };
2989
2990 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2991 {
2992 .pa_start = 0x480bd400,
2993 .pa_end = 0x480bd47f,
2994 .flags = ADDR_TYPE_RT,
2995 },
2996 { }
2997 };
2998
2999 /* l4_core -> mmu isp */
3000 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3001 .master = &omap3xxx_l4_core_hwmod,
3002 .slave = &omap3xxx_mmu_isp_hwmod,
3003 .addr = omap3xxx_mmu_isp_addrs,
3004 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005 };
3006
3007 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3008 .name = "mmu_isp",
3009 .class = &omap3xxx_mmu_hwmod_class,
3010 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3011 .main_clk = "cam_ick",
3012 .dev_attr = &mmu_isp_dev_attr,
3013 .flags = HWMOD_NO_IDLEST,
3014 };
3015
3016 /* mmu iva */
3017
3018 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3019 .nr_tlb_entries = 32,
3020 };
3021
3022 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3023 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3024 { .irq = 28 + OMAP_INTC_START, },
3025 { .irq = -1 }
3026 };
3027
3028 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3029 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3030 };
3031
3032 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3033 {
3034 .pa_start = 0x5d000000,
3035 .pa_end = 0x5d00007f,
3036 .flags = ADDR_TYPE_RT,
3037 },
3038 { }
3039 };
3040
3041 /* l3_main -> iva mmu */
3042 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3043 .master = &omap3xxx_l3_main_hwmod,
3044 .slave = &omap3xxx_mmu_iva_hwmod,
3045 .addr = omap3xxx_mmu_iva_addrs,
3046 .user = OCP_USER_MPU | OCP_USER_SDMA,
3047 };
3048
3049 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3050 .name = "mmu_iva",
3051 .class = &omap3xxx_mmu_hwmod_class,
3052 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3053 .clkdm_name = "iva2_clkdm",
3054 .rst_lines = omap3xxx_mmu_iva_resets,
3055 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3056 .main_clk = "iva2_ck",
3057 .prcm = {
3058 .omap2 = {
3059 .module_offs = OMAP3430_IVA2_MOD,
3060 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
3061 .idlest_reg_id = 1,
3062 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
3063 },
3064 },
3065 .dev_attr = &mmu_iva_dev_attr,
3066 .flags = HWMOD_NO_IDLEST,
3067 };
3068
3069 /* l4_per -> gpio4 */
3070 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3071 {
3072 .pa_start = 0x49054000,
3073 .pa_end = 0x490541ff,
3074 .flags = ADDR_TYPE_RT
3075 },
3076 { }
3077 };
3078
3079 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3080 .master = &omap3xxx_l4_per_hwmod,
3081 .slave = &omap3xxx_gpio4_hwmod,
3082 .addr = omap3xxx_gpio4_addrs,
3083 .user = OCP_USER_MPU | OCP_USER_SDMA,
3084 };
3085
3086 /* l4_per -> gpio5 */
3087 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3088 {
3089 .pa_start = 0x49056000,
3090 .pa_end = 0x490561ff,
3091 .flags = ADDR_TYPE_RT
3092 },
3093 { }
3094 };
3095
3096 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3097 .master = &omap3xxx_l4_per_hwmod,
3098 .slave = &omap3xxx_gpio5_hwmod,
3099 .addr = omap3xxx_gpio5_addrs,
3100 .user = OCP_USER_MPU | OCP_USER_SDMA,
3101 };
3102
3103 /* l4_per -> gpio6 */
3104 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3105 {
3106 .pa_start = 0x49058000,
3107 .pa_end = 0x490581ff,
3108 .flags = ADDR_TYPE_RT
3109 },
3110 { }
3111 };
3112
3113 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3114 .master = &omap3xxx_l4_per_hwmod,
3115 .slave = &omap3xxx_gpio6_hwmod,
3116 .addr = omap3xxx_gpio6_addrs,
3117 .user = OCP_USER_MPU | OCP_USER_SDMA,
3118 };
3119
3120 /* dma_system -> L3 */
3121 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3122 .master = &omap3xxx_dma_system_hwmod,
3123 .slave = &omap3xxx_l3_main_hwmod,
3124 .clk = "core_l3_ick",
3125 .user = OCP_USER_MPU | OCP_USER_SDMA,
3126 };
3127
3128 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3129 {
3130 .pa_start = 0x48056000,
3131 .pa_end = 0x48056fff,
3132 .flags = ADDR_TYPE_RT
3133 },
3134 { }
3135 };
3136
3137 /* l4_cfg -> dma_system */
3138 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3139 .master = &omap3xxx_l4_core_hwmod,
3140 .slave = &omap3xxx_dma_system_hwmod,
3141 .clk = "core_l4_ick",
3142 .addr = omap3xxx_dma_system_addrs,
3143 .user = OCP_USER_MPU | OCP_USER_SDMA,
3144 };
3145
3146 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3147 {
3148 .name = "mpu",
3149 .pa_start = 0x48074000,
3150 .pa_end = 0x480740ff,
3151 .flags = ADDR_TYPE_RT
3152 },
3153 { }
3154 };
3155
3156 /* l4_core -> mcbsp1 */
3157 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3158 .master = &omap3xxx_l4_core_hwmod,
3159 .slave = &omap3xxx_mcbsp1_hwmod,
3160 .clk = "mcbsp1_ick",
3161 .addr = omap3xxx_mcbsp1_addrs,
3162 .user = OCP_USER_MPU | OCP_USER_SDMA,
3163 };
3164
3165 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3166 {
3167 .name = "mpu",
3168 .pa_start = 0x49022000,
3169 .pa_end = 0x490220ff,
3170 .flags = ADDR_TYPE_RT
3171 },
3172 { }
3173 };
3174
3175 /* l4_per -> mcbsp2 */
3176 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3177 .master = &omap3xxx_l4_per_hwmod,
3178 .slave = &omap3xxx_mcbsp2_hwmod,
3179 .clk = "mcbsp2_ick",
3180 .addr = omap3xxx_mcbsp2_addrs,
3181 .user = OCP_USER_MPU | OCP_USER_SDMA,
3182 };
3183
3184 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3185 {
3186 .name = "mpu",
3187 .pa_start = 0x49024000,
3188 .pa_end = 0x490240ff,
3189 .flags = ADDR_TYPE_RT
3190 },
3191 { }
3192 };
3193
3194 /* l4_per -> mcbsp3 */
3195 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3196 .master = &omap3xxx_l4_per_hwmod,
3197 .slave = &omap3xxx_mcbsp3_hwmod,
3198 .clk = "mcbsp3_ick",
3199 .addr = omap3xxx_mcbsp3_addrs,
3200 .user = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3204 {
3205 .name = "mpu",
3206 .pa_start = 0x49026000,
3207 .pa_end = 0x490260ff,
3208 .flags = ADDR_TYPE_RT
3209 },
3210 { }
3211 };
3212
3213 /* l4_per -> mcbsp4 */
3214 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3215 .master = &omap3xxx_l4_per_hwmod,
3216 .slave = &omap3xxx_mcbsp4_hwmod,
3217 .clk = "mcbsp4_ick",
3218 .addr = omap3xxx_mcbsp4_addrs,
3219 .user = OCP_USER_MPU | OCP_USER_SDMA,
3220 };
3221
3222 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3223 {
3224 .name = "mpu",
3225 .pa_start = 0x48096000,
3226 .pa_end = 0x480960ff,
3227 .flags = ADDR_TYPE_RT
3228 },
3229 { }
3230 };
3231
3232 /* l4_core -> mcbsp5 */
3233 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3234 .master = &omap3xxx_l4_core_hwmod,
3235 .slave = &omap3xxx_mcbsp5_hwmod,
3236 .clk = "mcbsp5_ick",
3237 .addr = omap3xxx_mcbsp5_addrs,
3238 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239 };
3240
3241 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3242 {
3243 .name = "sidetone",
3244 .pa_start = 0x49028000,
3245 .pa_end = 0x490280ff,
3246 .flags = ADDR_TYPE_RT
3247 },
3248 { }
3249 };
3250
3251 /* l4_per -> mcbsp2_sidetone */
3252 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3253 .master = &omap3xxx_l4_per_hwmod,
3254 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3255 .clk = "mcbsp2_ick",
3256 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3257 .user = OCP_USER_MPU,
3258 };
3259
3260 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3261 {
3262 .name = "sidetone",
3263 .pa_start = 0x4902A000,
3264 .pa_end = 0x4902A0ff,
3265 .flags = ADDR_TYPE_RT
3266 },
3267 { }
3268 };
3269
3270 /* l4_per -> mcbsp3_sidetone */
3271 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3272 .master = &omap3xxx_l4_per_hwmod,
3273 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3274 .clk = "mcbsp3_ick",
3275 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3276 .user = OCP_USER_MPU,
3277 };
3278
3279 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3280 {
3281 .pa_start = 0x48094000,
3282 .pa_end = 0x480941ff,
3283 .flags = ADDR_TYPE_RT,
3284 },
3285 { }
3286 };
3287
3288 /* l4_core -> mailbox */
3289 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3290 .master = &omap3xxx_l4_core_hwmod,
3291 .slave = &omap3xxx_mailbox_hwmod,
3292 .addr = omap3xxx_mailbox_addrs,
3293 .user = OCP_USER_MPU | OCP_USER_SDMA,
3294 };
3295
3296 /* l4 core -> mcspi1 interface */
3297 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3298 .master = &omap3xxx_l4_core_hwmod,
3299 .slave = &omap34xx_mcspi1,
3300 .clk = "mcspi1_ick",
3301 .addr = omap2_mcspi1_addr_space,
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303 };
3304
3305 /* l4 core -> mcspi2 interface */
3306 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3307 .master = &omap3xxx_l4_core_hwmod,
3308 .slave = &omap34xx_mcspi2,
3309 .clk = "mcspi2_ick",
3310 .addr = omap2_mcspi2_addr_space,
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* l4 core -> mcspi3 interface */
3315 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3316 .master = &omap3xxx_l4_core_hwmod,
3317 .slave = &omap34xx_mcspi3,
3318 .clk = "mcspi3_ick",
3319 .addr = omap2430_mcspi3_addr_space,
3320 .user = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* l4 core -> mcspi4 interface */
3324 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3325 {
3326 .pa_start = 0x480ba000,
3327 .pa_end = 0x480ba0ff,
3328 .flags = ADDR_TYPE_RT,
3329 },
3330 { }
3331 };
3332
3333 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3334 .master = &omap3xxx_l4_core_hwmod,
3335 .slave = &omap34xx_mcspi4,
3336 .clk = "mcspi4_ick",
3337 .addr = omap34xx_mcspi4_addr_space,
3338 .user = OCP_USER_MPU | OCP_USER_SDMA,
3339 };
3340
3341 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3342 .master = &omap3xxx_usb_host_hs_hwmod,
3343 .slave = &omap3xxx_l3_main_hwmod,
3344 .clk = "core_l3_ick",
3345 .user = OCP_USER_MPU,
3346 };
3347
3348 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3349 {
3350 .name = "uhh",
3351 .pa_start = 0x48064000,
3352 .pa_end = 0x480643ff,
3353 .flags = ADDR_TYPE_RT
3354 },
3355 {
3356 .name = "ohci",
3357 .pa_start = 0x48064400,
3358 .pa_end = 0x480647ff,
3359 },
3360 {
3361 .name = "ehci",
3362 .pa_start = 0x48064800,
3363 .pa_end = 0x48064cff,
3364 },
3365 {}
3366 };
3367
3368 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3369 .master = &omap3xxx_l4_core_hwmod,
3370 .slave = &omap3xxx_usb_host_hs_hwmod,
3371 .clk = "usbhost_ick",
3372 .addr = omap3xxx_usb_host_hs_addrs,
3373 .user = OCP_USER_MPU | OCP_USER_SDMA,
3374 };
3375
3376 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3377 {
3378 .name = "tll",
3379 .pa_start = 0x48062000,
3380 .pa_end = 0x48062fff,
3381 .flags = ADDR_TYPE_RT
3382 },
3383 {}
3384 };
3385
3386 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3387 .master = &omap3xxx_l4_core_hwmod,
3388 .slave = &omap3xxx_usb_tll_hs_hwmod,
3389 .clk = "usbtll_ick",
3390 .addr = omap3xxx_usb_tll_hs_addrs,
3391 .user = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3393
3394 /* l4_core -> hdq1w interface */
3395 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3396 .master = &omap3xxx_l4_core_hwmod,
3397 .slave = &omap3xxx_hdq1w_hwmod,
3398 .clk = "hdq_ick",
3399 .addr = omap2_hdq1w_addr_space,
3400 .user = OCP_USER_MPU | OCP_USER_SDMA,
3401 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3402 };
3403
3404 /* l4_wkup -> 32ksync_counter */
3405 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3406 {
3407 .pa_start = 0x48320000,
3408 .pa_end = 0x4832001f,
3409 .flags = ADDR_TYPE_RT
3410 },
3411 { }
3412 };
3413
3414 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3415 {
3416 .pa_start = 0x6e000000,
3417 .pa_end = 0x6e000fff,
3418 .flags = ADDR_TYPE_RT
3419 },
3420 { }
3421 };
3422
3423 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3424 .master = &omap3xxx_l4_wkup_hwmod,
3425 .slave = &omap3xxx_counter_32k_hwmod,
3426 .clk = "omap_32ksync_ick",
3427 .addr = omap3xxx_counter_32k_addrs,
3428 .user = OCP_USER_MPU | OCP_USER_SDMA,
3429 };
3430
3431 /* am35xx has Davinci MDIO & EMAC */
3432 static struct omap_hwmod_class am35xx_mdio_class = {
3433 .name = "davinci_mdio",
3434 };
3435
3436 static struct omap_hwmod am35xx_mdio_hwmod = {
3437 .name = "davinci_mdio",
3438 .class = &am35xx_mdio_class,
3439 .flags = HWMOD_NO_IDLEST,
3440 };
3441
3442 /*
3443 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3444 * but this will probably require some additional hwmod core support,
3445 * so is left as a future to-do item.
3446 */
3447 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3448 .master = &am35xx_mdio_hwmod,
3449 .slave = &omap3xxx_l3_main_hwmod,
3450 .clk = "emac_fck",
3451 .user = OCP_USER_MPU,
3452 };
3453
3454 /* l4_core -> davinci mdio */
3455 /*
3456 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3457 * but this will probably require some additional hwmod core support,
3458 * so is left as a future to-do item.
3459 */
3460 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3461 .master = &omap3xxx_l4_core_hwmod,
3462 .slave = &am35xx_mdio_hwmod,
3463 .clk = "emac_fck",
3464 .user = OCP_USER_MPU,
3465 };
3466
3467 static struct omap_hwmod_class am35xx_emac_class = {
3468 .name = "davinci_emac",
3469 };
3470
3471 static struct omap_hwmod am35xx_emac_hwmod = {
3472 .name = "davinci_emac",
3473 .class = &am35xx_emac_class,
3474 /*
3475 * According to Mark Greer, the MPU will not return from WFI
3476 * when the EMAC signals an interrupt.
3477 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3478 */
3479 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3480 };
3481
3482 /* l3_core -> davinci emac interface */
3483 /*
3484 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3485 * but this will probably require some additional hwmod core support,
3486 * so is left as a future to-do item.
3487 */
3488 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3489 .master = &am35xx_emac_hwmod,
3490 .slave = &omap3xxx_l3_main_hwmod,
3491 .clk = "emac_ick",
3492 .user = OCP_USER_MPU,
3493 };
3494
3495 /* l4_core -> davinci emac */
3496 /*
3497 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3498 * but this will probably require some additional hwmod core support,
3499 * so is left as a future to-do item.
3500 */
3501 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3502 .master = &omap3xxx_l4_core_hwmod,
3503 .slave = &am35xx_emac_hwmod,
3504 .clk = "emac_ick",
3505 .user = OCP_USER_MPU,
3506 };
3507
3508 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3509 .master = &omap3xxx_l3_main_hwmod,
3510 .slave = &omap3xxx_gpmc_hwmod,
3511 .clk = "core_l3_ick",
3512 .addr = omap3xxx_gpmc_addrs,
3513 .user = OCP_USER_MPU | OCP_USER_SDMA,
3514 };
3515
3516 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3517 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3518 .sidle_shift = 4,
3519 .srst_shift = 1,
3520 .autoidle_shift = 0,
3521 };
3522
3523 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3524 .rev_offs = 0x5c,
3525 .sysc_offs = 0x60,
3526 .syss_offs = 0x64,
3527 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3528 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3529 .sysc_fields = &omap3_sham_sysc_fields,
3530 };
3531
3532 static struct omap_hwmod_class omap3xxx_sham_class = {
3533 .name = "sham",
3534 .sysc = &omap3_sham_sysc,
3535 };
3536
3537 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3538 { .irq = 49 + OMAP_INTC_START, },
3539 { .irq = -1 }
3540 };
3541
3542 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3543 { .name = "rx", .dma_req = 69, },
3544 { .dma_req = -1 }
3545 };
3546
3547 static struct omap_hwmod omap3xxx_sham_hwmod = {
3548 .name = "sham",
3549 .mpu_irqs = omap3_sham_mpu_irqs,
3550 .sdma_reqs = omap3_sham_sdma_reqs,
3551 .main_clk = "sha12_ick",
3552 .prcm = {
3553 .omap2 = {
3554 .module_offs = CORE_MOD,
3555 .prcm_reg_id = 1,
3556 .module_bit = OMAP3430_EN_SHA12_SHIFT,
3557 .idlest_reg_id = 1,
3558 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3559 },
3560 },
3561 .class = &omap3xxx_sham_class,
3562 };
3563
3564 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3565 {
3566 .pa_start = 0x480c3000,
3567 .pa_end = 0x480c3000 + 0x64 - 1,
3568 .flags = ADDR_TYPE_RT
3569 },
3570 { }
3571 };
3572
3573 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3574 .master = &omap3xxx_l4_core_hwmod,
3575 .slave = &omap3xxx_sham_hwmod,
3576 .clk = "sha12_ick",
3577 .addr = omap3xxx_sham_addrs,
3578 .user = OCP_USER_MPU | OCP_USER_SDMA,
3579 };
3580
3581 /* l4_core -> AES */
3582 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3583 .sidle_shift = 6,
3584 .srst_shift = 1,
3585 .autoidle_shift = 0,
3586 };
3587
3588 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3589 .rev_offs = 0x44,
3590 .sysc_offs = 0x48,
3591 .syss_offs = 0x4c,
3592 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3593 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3594 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3595 .sysc_fields = &omap3xxx_aes_sysc_fields,
3596 };
3597
3598 static struct omap_hwmod_class omap3xxx_aes_class = {
3599 .name = "aes",
3600 .sysc = &omap3_aes_sysc,
3601 };
3602
3603 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3604 { .name = "tx", .dma_req = 65, },
3605 { .name = "rx", .dma_req = 66, },
3606 { .dma_req = -1 }
3607 };
3608
3609 static struct omap_hwmod omap3xxx_aes_hwmod = {
3610 .name = "aes",
3611 .sdma_reqs = omap3_aes_sdma_reqs,
3612 .main_clk = "aes2_ick",
3613 .prcm = {
3614 .omap2 = {
3615 .module_offs = CORE_MOD,
3616 .prcm_reg_id = 1,
3617 .module_bit = OMAP3430_EN_AES2_SHIFT,
3618 .idlest_reg_id = 1,
3619 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3620 },
3621 },
3622 .class = &omap3xxx_aes_class,
3623 };
3624
3625 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3626 {
3627 .pa_start = 0x480c5000,
3628 .pa_end = 0x480c5000 + 0x50 - 1,
3629 .flags = ADDR_TYPE_RT
3630 },
3631 { }
3632 };
3633
3634 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3635 .master = &omap3xxx_l4_core_hwmod,
3636 .slave = &omap3xxx_aes_hwmod,
3637 .clk = "aes2_ick",
3638 .addr = omap3xxx_aes_addrs,
3639 .user = OCP_USER_MPU | OCP_USER_SDMA,
3640 };
3641
3642 /*
3643 * 'ssi' class
3644 * synchronous serial interface (multichannel and full-duplex serial if)
3645 */
3646
3647 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3648 .rev_offs = 0x0000,
3649 .sysc_offs = 0x0010,
3650 .syss_offs = 0x0014,
3651 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
3652 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3654 .sysc_fields = &omap_hwmod_sysc_type1,
3655 };
3656
3657 static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
3658 .name = "ssi",
3659 .sysc = &omap34xx_ssi_sysc,
3660 };
3661
3662 static struct omap_hwmod omap34xx_ssi_hwmod = {
3663 .name = "ssi",
3664 .class = &omap34xx_ssi_hwmod_class,
3665 .clkdm_name = "core_l4_clkdm",
3666 .main_clk = "ssi_ssr_fck",
3667 .prcm = {
3668 .omap2 = {
3669 .prcm_reg_id = 1,
3670 .module_bit = OMAP3430_EN_SSI_SHIFT,
3671 .module_offs = CORE_MOD,
3672 .idlest_reg_id = 1,
3673 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
3674 },
3675 },
3676 };
3677
3678 /* L4 CORE -> SSI */
3679 static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
3680 .master = &omap3xxx_l4_core_hwmod,
3681 .slave = &omap34xx_ssi_hwmod,
3682 .clk = "ssi_ick",
3683 .user = OCP_USER_MPU | OCP_USER_SDMA,
3684 };
3685
3686 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3687 &omap3xxx_l3_main__l4_core,
3688 &omap3xxx_l3_main__l4_per,
3689 &omap3xxx_mpu__l3_main,
3690 &omap3xxx_l3_main__l4_debugss,
3691 &omap3xxx_l4_core__l4_wkup,
3692 &omap3xxx_l4_core__mmc3,
3693 &omap3_l4_core__uart1,
3694 &omap3_l4_core__uart2,
3695 &omap3_l4_per__uart3,
3696 &omap3_l4_core__i2c1,
3697 &omap3_l4_core__i2c2,
3698 &omap3_l4_core__i2c3,
3699 &omap3xxx_l4_wkup__l4_sec,
3700 &omap3xxx_l4_wkup__timer1,
3701 &omap3xxx_l4_per__timer2,
3702 &omap3xxx_l4_per__timer3,
3703 &omap3xxx_l4_per__timer4,
3704 &omap3xxx_l4_per__timer5,
3705 &omap3xxx_l4_per__timer6,
3706 &omap3xxx_l4_per__timer7,
3707 &omap3xxx_l4_per__timer8,
3708 &omap3xxx_l4_per__timer9,
3709 &omap3xxx_l4_core__timer10,
3710 &omap3xxx_l4_core__timer11,
3711 &omap3xxx_l4_wkup__wd_timer2,
3712 &omap3xxx_l4_wkup__gpio1,
3713 &omap3xxx_l4_per__gpio2,
3714 &omap3xxx_l4_per__gpio3,
3715 &omap3xxx_l4_per__gpio4,
3716 &omap3xxx_l4_per__gpio5,
3717 &omap3xxx_l4_per__gpio6,
3718 &omap3xxx_dma_system__l3,
3719 &omap3xxx_l4_core__dma_system,
3720 &omap3xxx_l4_core__mcbsp1,
3721 &omap3xxx_l4_per__mcbsp2,
3722 &omap3xxx_l4_per__mcbsp3,
3723 &omap3xxx_l4_per__mcbsp4,
3724 &omap3xxx_l4_core__mcbsp5,
3725 &omap3xxx_l4_per__mcbsp2_sidetone,
3726 &omap3xxx_l4_per__mcbsp3_sidetone,
3727 &omap34xx_l4_core__mcspi1,
3728 &omap34xx_l4_core__mcspi2,
3729 &omap34xx_l4_core__mcspi3,
3730 &omap34xx_l4_core__mcspi4,
3731 &omap3xxx_l4_wkup__counter_32k,
3732 &omap3xxx_l3_main__gpmc,
3733 NULL,
3734 };
3735
3736 /* GP-only hwmod links */
3737 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3738 &omap3xxx_l4_sec__timer12,
3739 NULL
3740 };
3741
3742 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3743 &omap3xxx_l4_sec__timer12,
3744 NULL
3745 };
3746
3747 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3748 &omap3xxx_l4_sec__timer12,
3749 NULL
3750 };
3751
3752 /* crypto hwmod links */
3753 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3754 &omap3xxx_l4_core__sham,
3755 NULL
3756 };
3757
3758 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3759 &omap3xxx_l4_core__aes,
3760 NULL
3761 };
3762
3763 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
3764 &omap3xxx_l4_core__sham,
3765 NULL
3766 };
3767
3768 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
3769 &omap3xxx_l4_core__aes,
3770 NULL
3771 };
3772
3773 /*
3774 * Apparently the SHA/MD5 and AES accelerator IP blocks are
3775 * only present on some AM35xx chips, and no one knows which
3776 * ones. See
3777 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3778 * if you need these IP blocks on an AM35xx, try uncommenting
3779 * the following lines.
3780 */
3781 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3782 /* &omap3xxx_l4_core__sham, */
3783 NULL
3784 };
3785
3786 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3787 /* &omap3xxx_l4_core__aes, */
3788 NULL
3789 };
3790
3791 /* 3430ES1-only hwmod links */
3792 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3793 &omap3430es1_dss__l3,
3794 &omap3430es1_l4_core__dss,
3795 NULL
3796 };
3797
3798 /* 3430ES2+-only hwmod links */
3799 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3800 &omap3xxx_dss__l3,
3801 &omap3xxx_l4_core__dss,
3802 &omap3xxx_usbhsotg__l3,
3803 &omap3xxx_l4_core__usbhsotg,
3804 &omap3xxx_usb_host_hs__l3_main_2,
3805 &omap3xxx_l4_core__usb_host_hs,
3806 &omap3xxx_l4_core__usb_tll_hs,
3807 NULL
3808 };
3809
3810 /* <= 3430ES3-only hwmod links */
3811 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3812 &omap3xxx_l4_core__pre_es3_mmc1,
3813 &omap3xxx_l4_core__pre_es3_mmc2,
3814 NULL
3815 };
3816
3817 /* 3430ES3+-only hwmod links */
3818 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3819 &omap3xxx_l4_core__es3plus_mmc1,
3820 &omap3xxx_l4_core__es3plus_mmc2,
3821 NULL
3822 };
3823
3824 /* 34xx-only hwmod links (all ES revisions) */
3825 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3826 &omap3xxx_l3__iva,
3827 &omap34xx_l4_core__sr1,
3828 &omap34xx_l4_core__sr2,
3829 &omap3xxx_l4_core__mailbox,
3830 &omap3xxx_l4_core__hdq1w,
3831 &omap3xxx_sad2d__l3,
3832 &omap3xxx_l4_core__mmu_isp,
3833 &omap3xxx_l3_main__mmu_iva,
3834 &omap34xx_l4_core__ssi,
3835 NULL
3836 };
3837
3838 /* 36xx-only hwmod links (all ES revisions) */
3839 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3840 &omap3xxx_l3__iva,
3841 &omap36xx_l4_per__uart4,
3842 &omap3xxx_dss__l3,
3843 &omap3xxx_l4_core__dss,
3844 &omap36xx_l4_core__sr1,
3845 &omap36xx_l4_core__sr2,
3846 &omap3xxx_usbhsotg__l3,
3847 &omap3xxx_l4_core__usbhsotg,
3848 &omap3xxx_l4_core__mailbox,
3849 &omap3xxx_usb_host_hs__l3_main_2,
3850 &omap3xxx_l4_core__usb_host_hs,
3851 &omap3xxx_l4_core__usb_tll_hs,
3852 &omap3xxx_l4_core__es3plus_mmc1,
3853 &omap3xxx_l4_core__es3plus_mmc2,
3854 &omap3xxx_l4_core__hdq1w,
3855 &omap3xxx_sad2d__l3,
3856 &omap3xxx_l4_core__mmu_isp,
3857 &omap3xxx_l3_main__mmu_iva,
3858 NULL
3859 };
3860
3861 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3862 &omap3xxx_dss__l3,
3863 &omap3xxx_l4_core__dss,
3864 &am35xx_usbhsotg__l3,
3865 &am35xx_l4_core__usbhsotg,
3866 &am35xx_l4_core__uart4,
3867 &omap3xxx_usb_host_hs__l3_main_2,
3868 &omap3xxx_l4_core__usb_host_hs,
3869 &omap3xxx_l4_core__usb_tll_hs,
3870 &omap3xxx_l4_core__es3plus_mmc1,
3871 &omap3xxx_l4_core__es3plus_mmc2,
3872 &omap3xxx_l4_core__hdq1w,
3873 &am35xx_mdio__l3,
3874 &am35xx_l4_core__mdio,
3875 &am35xx_emac__l3,
3876 &am35xx_l4_core__emac,
3877 NULL
3878 };
3879
3880 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3881 &omap3xxx_l4_core__dss_dispc,
3882 &omap3xxx_l4_core__dss_dsi1,
3883 &omap3xxx_l4_core__dss_rfbi,
3884 &omap3xxx_l4_core__dss_venc,
3885 NULL
3886 };
3887
3888 /**
3889 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3890 * @bus: struct device_node * for the top-level OMAP DT data
3891 * @dev_name: device name used in the DT file
3892 *
3893 * Determine whether a "secure" IP block @dev_name is usable by Linux.
3894 * There doesn't appear to be a 100% reliable way to determine this,
3895 * so we rely on heuristics. If @bus is null, meaning there's no DT
3896 * data, then we only assume the IP block is accessible if the OMAP is
3897 * fused as a 'general-purpose' SoC. If however DT data is present,
3898 * test to see if the IP block is described in the DT data and set to
3899 * 'status = "okay"'. If so then we assume the ODM has configured the
3900 * OMAP firewalls to allow access to the IP block.
3901 *
3902 * Return: 0 if device named @dev_name is not likely to be accessible,
3903 * or 1 if it is likely to be accessible.
3904 */
3905 static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3906 const char *dev_name)
3907 {
3908 if (!bus)
3909 return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
3910
3911 if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
3912 return 1;
3913
3914 return 0;
3915 }
3916
3917 int __init omap3xxx_hwmod_init(void)
3918 {
3919 int r;
3920 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3921 struct omap_hwmod_ocp_if **h_aes = NULL;
3922 struct device_node *bus = NULL;
3923 unsigned int rev;
3924
3925 omap_hwmod_init();
3926
3927 /* Register hwmod links common to all OMAP3 */
3928 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3929 if (r < 0)
3930 return r;
3931
3932 rev = omap_rev();
3933
3934 /*
3935 * Register hwmod links common to individual OMAP3 families, all
3936 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3937 * All possible revisions should be included in this conditional.
3938 */
3939 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3940 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3941 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3942 h = omap34xx_hwmod_ocp_ifs;
3943 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3944 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3945 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3946 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3947 h = am35xx_hwmod_ocp_ifs;
3948 h_gp = am35xx_gp_hwmod_ocp_ifs;
3949 h_sham = am35xx_sham_hwmod_ocp_ifs;
3950 h_aes = am35xx_aes_hwmod_ocp_ifs;
3951 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3952 rev == OMAP3630_REV_ES1_2) {
3953 h = omap36xx_hwmod_ocp_ifs;
3954 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3955 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3956 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3957 } else {
3958 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3959 return -EINVAL;
3960 }
3961
3962 r = omap_hwmod_register_links(h);
3963 if (r < 0)
3964 return r;
3965
3966 /* Register GP-only hwmod links. */
3967 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3968 r = omap_hwmod_register_links(h_gp);
3969 if (r < 0)
3970 return r;
3971 }
3972
3973 /*
3974 * Register crypto hwmod links only if they are not disabled in DT.
3975 * If DT information is missing, enable them only for GP devices.
3976 */
3977
3978 if (of_have_populated_dt())
3979 bus = of_find_node_by_name(NULL, "ocp");
3980
3981 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3982 r = omap_hwmod_register_links(h_sham);
3983 if (r < 0)
3984 return r;
3985 }
3986
3987 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3988 r = omap_hwmod_register_links(h_aes);
3989 if (r < 0)
3990 return r;
3991 }
3992
3993 /*
3994 * Register hwmod links specific to certain ES levels of a
3995 * particular family of silicon (e.g., 34xx ES1.0)
3996 */
3997 h = NULL;
3998 if (rev == OMAP3430_REV_ES1_0) {
3999 h = omap3430es1_hwmod_ocp_ifs;
4000 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
4001 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
4002 rev == OMAP3430_REV_ES3_1_2) {
4003 h = omap3430es2plus_hwmod_ocp_ifs;
4004 }
4005
4006 if (h) {
4007 r = omap_hwmod_register_links(h);
4008 if (r < 0)
4009 return r;
4010 }
4011
4012 h = NULL;
4013 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
4014 rev == OMAP3430_REV_ES2_1) {
4015 h = omap3430_pre_es3_hwmod_ocp_ifs;
4016 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
4017 rev == OMAP3430_REV_ES3_1_2) {
4018 h = omap3430_es3plus_hwmod_ocp_ifs;
4019 }
4020
4021 if (h)
4022 r = omap_hwmod_register_links(h);
4023 if (r < 0)
4024 return r;
4025
4026 /*
4027 * DSS code presumes that dss_core hwmod is handled first,
4028 * _before_ any other DSS related hwmods so register common
4029 * DSS hwmod links last to ensure that dss_core is already
4030 * registered. Otherwise some change things may happen, for
4031 * ex. if dispc is handled before dss_core and DSS is enabled
4032 * in bootloader DISPC will be reset with outputs enabled
4033 * which sometimes leads to unrecoverable L3 error. XXX The
4034 * long-term fix to this is to ensure hwmods are set up in
4035 * dependency order in the hwmod core code.
4036 */
4037 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
4038
4039 return r;
4040 }
CRIS linux kernel tree