?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
blk: rq_data_dir() should not return a boolean
[cris-mirror.git] / arch / arm / mach-shmobile / setup-r8a7778.c
blobb9116c81e54beb1dfdbd8f01a66f9d2941e2d137
1 /*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk/shmobile.h>
19 #include <linux/kernel.h>
20 #include <linux/io.h>
21 #include <linux/irqchip/arm-gic.h>
22 #include <linux/of.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_data/dma-rcar-hpbdma.h>
25 #include <linux/platform_data/gpio-rcar.h>
26 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
27 #include <linux/platform_device.h>
28 #include <linux/irqchip.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_timer.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/usb/phy.h>
33 #include <linux/usb/hcd.h>
34 #include <linux/usb/ehci_pdriver.h>
35 #include <linux/usb/ohci_pdriver.h>
36 #include <linux/dma-mapping.h>
37
38 #include <asm/mach/arch.h>
39 #include <asm/hardware/cache-l2x0.h>
40
41 #include "common.h"
42 #include "irqs.h"
43 #include "r8a7778.h"
44
45 #define MODEMR 0xffcc0020
46
47 #ifdef CONFIG_COMMON_CLK
48 static void __init r8a7778_timer_init(void)
49 {
50 u32 mode;
51 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
52
53 BUG_ON(!modemr);
54 mode = ioread32(modemr);
55 iounmap(modemr);
56 r8a7778_clocks_init(mode);
57 }
58 #endif
59
60 /* SCIF */
61 #define R8A7778_SCIF(index, baseaddr, irq) \
62 static struct plat_sci_port scif##index##_platform_data = { \
63 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
64 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
65 .type = PORT_SCIF, \
66 }; \
67 \
68 static struct resource scif##index##_resources[] = { \
69 DEFINE_RES_MEM(baseaddr, 0x100), \
70 DEFINE_RES_IRQ(irq), \
71 }
72
73 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
74 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
75 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
76 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
77 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
78 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
79
80 #define r8a7778_register_scif(index) \
81 platform_device_register_resndata(NULL, "sh-sci", index, \
82 scif##index##_resources, \
83 ARRAY_SIZE(scif##index##_resources), \
84 &scif##index##_platform_data, \
85 sizeof(scif##index##_platform_data))
86
87 /* TMU */
88 static struct sh_timer_config sh_tmu0_platform_data = {
89 .channels_mask = 7,
90 };
91
92 static struct resource sh_tmu0_resources[] = {
93 DEFINE_RES_MEM(0xffd80000, 0x30),
94 DEFINE_RES_IRQ(gic_iid(0x40)),
95 DEFINE_RES_IRQ(gic_iid(0x41)),
96 DEFINE_RES_IRQ(gic_iid(0x42)),
97 };
98
99 #define r8a7778_register_tmu(idx) \
100 platform_device_register_resndata( \
101 NULL, "sh-tmu", idx, \
102 sh_tmu##idx##_resources, \
103 ARRAY_SIZE(sh_tmu##idx##_resources), \
104 &sh_tmu##idx##_platform_data, \
105 sizeof(sh_tmu##idx##_platform_data))
106
107 int r8a7778_usb_phy_power(bool enable)
108 {
109 static struct usb_phy *phy = NULL;
110 int ret = 0;
111
112 if (!phy)
113 phy = usb_get_phy(USB_PHY_TYPE_USB2);
114
115 if (IS_ERR(phy)) {
116 pr_err("kernel doesn't have usb phy driver\n");
117 return PTR_ERR(phy);
118 }
119
120 if (enable)
121 ret = usb_phy_init(phy);
122 else
123 usb_phy_shutdown(phy);
124
125 return ret;
126 }
127
128 /* USB */
129 static int usb_power_on(struct platform_device *pdev)
130 {
131 int ret = r8a7778_usb_phy_power(true);
132
133 if (ret)
134 return ret;
135
136 pm_runtime_enable(&pdev->dev);
137 pm_runtime_get_sync(&pdev->dev);
138
139 return 0;
140 }
141
142 static void usb_power_off(struct platform_device *pdev)
143 {
144 if (r8a7778_usb_phy_power(false))
145 return;
146
147 pm_runtime_put_sync(&pdev->dev);
148 pm_runtime_disable(&pdev->dev);
149 }
150
151 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
152 {
153 /*
154 * Below are recommended values from the datasheet;
155 * see [USB :: Setting of EHCI Internal Buffer].
156 */
157 /* EHCI IP internal buffer setting */
158 iowrite32(0x00ff0040, hcd->regs + 0x0094);
159 /* EHCI IP internal buffer enable */
160 iowrite32(0x00000001, hcd->regs + 0x009C);
161
162 return 0;
163 }
164
165 static struct usb_ehci_pdata ehci_pdata __initdata = {
166 .power_on = usb_power_on,
167 .power_off = usb_power_off,
168 .power_suspend = usb_power_off,
169 .pre_setup = ehci_init_internal_buffer,
170 };
171
172 static struct resource ehci_resources[] __initdata = {
173 DEFINE_RES_MEM(0xffe70000, 0x400),
174 DEFINE_RES_IRQ(gic_iid(0x4c)),
175 };
176
177 static struct usb_ohci_pdata ohci_pdata __initdata = {
178 .power_on = usb_power_on,
179 .power_off = usb_power_off,
180 .power_suspend = usb_power_off,
181 };
182
183 static struct resource ohci_resources[] __initdata = {
184 DEFINE_RES_MEM(0xffe70400, 0x400),
185 DEFINE_RES_IRQ(gic_iid(0x4c)),
186 };
187
188 #define USB_PLATFORM_INFO(hci) \
189 static struct platform_device_info hci##_info __initdata = { \
190 .name = #hci "-platform", \
191 .id = -1, \
192 .res = hci##_resources, \
193 .num_res = ARRAY_SIZE(hci##_resources), \
194 .data = &hci##_pdata, \
195 .size_data = sizeof(hci##_pdata), \
196 .dma_mask = DMA_BIT_MASK(32), \
197 }
198
199 USB_PLATFORM_INFO(ehci);
200 USB_PLATFORM_INFO(ohci);
201
202 /* PFC/GPIO */
203 static struct resource pfc_resources[] __initdata = {
204 DEFINE_RES_MEM(0xfffc0000, 0x118),
205 };
206
207 #define R8A7778_GPIO(idx) \
208 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
209 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
210 DEFINE_RES_IRQ(gic_iid(0x87)), \
211 }; \
212 \
213 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
214 .gpio_base = 32 * (idx), \
215 .irq_base = GPIO_IRQ_BASE(idx), \
216 .number_of_pins = 32, \
217 .pctl_name = "pfc-r8a7778", \
218 }
219
220 R8A7778_GPIO(0);
221 R8A7778_GPIO(1);
222 R8A7778_GPIO(2);
223 R8A7778_GPIO(3);
224 R8A7778_GPIO(4);
225
226 #define r8a7778_register_gpio(idx) \
227 platform_device_register_resndata( \
228 NULL, "gpio_rcar", idx, \
229 r8a7778_gpio##idx##_resources, \
230 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \
231 &r8a7778_gpio##idx##_platform_data, \
232 sizeof(r8a7778_gpio##idx##_platform_data))
233
234 void __init r8a7778_pinmux_init(void)
235 {
236 platform_device_register_simple(
237 "pfc-r8a7778", -1,
238 pfc_resources,
239 ARRAY_SIZE(pfc_resources));
240
241 r8a7778_register_gpio(0);
242 r8a7778_register_gpio(1);
243 r8a7778_register_gpio(2);
244 r8a7778_register_gpio(3);
245 r8a7778_register_gpio(4);
246 };
247
248 /* I2C */
249 static struct resource i2c_resources[] __initdata = {
250 /* I2C0 */
251 DEFINE_RES_MEM(0xffc70000, 0x1000),
252 DEFINE_RES_IRQ(gic_iid(0x63)),
253 /* I2C1 */
254 DEFINE_RES_MEM(0xffc71000, 0x1000),
255 DEFINE_RES_IRQ(gic_iid(0x6e)),
256 /* I2C2 */
257 DEFINE_RES_MEM(0xffc72000, 0x1000),
258 DEFINE_RES_IRQ(gic_iid(0x6c)),
259 /* I2C3 */
260 DEFINE_RES_MEM(0xffc73000, 0x1000),
261 DEFINE_RES_IRQ(gic_iid(0x6d)),
262 };
263
264 static void __init r8a7778_register_i2c(int id)
265 {
266 BUG_ON(id < 0 || id > 3);
267
268 platform_device_register_simple(
269 "i2c-rcar", id,
270 i2c_resources + (2 * id), 2);
271 }
272
273 /* HSPI */
274 static struct resource hspi_resources[] __initdata = {
275 /* HSPI0 */
276 DEFINE_RES_MEM(0xfffc7000, 0x18),
277 DEFINE_RES_IRQ(gic_iid(0x5f)),
278 /* HSPI1 */
279 DEFINE_RES_MEM(0xfffc8000, 0x18),
280 DEFINE_RES_IRQ(gic_iid(0x74)),
281 /* HSPI2 */
282 DEFINE_RES_MEM(0xfffc6000, 0x18),
283 DEFINE_RES_IRQ(gic_iid(0x75)),
284 };
285
286 static void __init r8a7778_register_hspi(int id)
287 {
288 BUG_ON(id < 0 || id > 2);
289
290 platform_device_register_simple(
291 "sh-hspi", id,
292 hspi_resources + (2 * id), 2);
293 }
294
295 void __init r8a7778_add_dt_devices(void)
296 {
297 #ifdef CONFIG_CACHE_L2X0
298 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
299 if (base) {
300 /*
301 * Shared attribute override enable, 64K*16way
302 * don't call iounmap(base)
303 */
304 l2x0_init(base, 0x00400000, 0xc20f0fff);
305 }
306 #endif
307 }
308
309 /* HPB-DMA */
310
311 /* Asynchronous mode register (ASYNCMDR) bits */
312 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */
313 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */
314 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
315 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */
316 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
317 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
318
319 #define HPBDMA_SSI(_id) \
320 { \
321 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \
322 .addr = 0xffd91008 + (_id * 0x40), \
323 .dcr = HPB_DMAE_DCR_CT | \
324 HPB_DMAE_DCR_DIP | \
325 HPB_DMAE_DCR_SPDS_32BIT | \
326 HPB_DMAE_DCR_DMDL | \
327 HPB_DMAE_DCR_DPDS_32BIT, \
328 .port = _id + (_id << 8), \
329 .dma_ch = (28 + _id), \
330 }, { \
331 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \
332 .addr = 0xffd9100c + (_id * 0x40), \
333 .dcr = HPB_DMAE_DCR_CT | \
334 HPB_DMAE_DCR_DIP | \
335 HPB_DMAE_DCR_SMDL | \
336 HPB_DMAE_DCR_SPDS_32BIT | \
337 HPB_DMAE_DCR_DPDS_32BIT, \
338 .port = _id + (_id << 8), \
339 .dma_ch = (28 + _id), \
340 }
341
342 #define HPBDMA_HPBIF(_id) \
343 { \
344 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
345 .addr = 0xffda0000 + (_id * 0x1000), \
346 .dcr = HPB_DMAE_DCR_CT | \
347 HPB_DMAE_DCR_DIP | \
348 HPB_DMAE_DCR_SPDS_32BIT | \
349 HPB_DMAE_DCR_DMDL | \
350 HPB_DMAE_DCR_DPDS_32BIT, \
351 .port = 0x1111, \
352 .dma_ch = (28 + _id), \
353 }, { \
354 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
355 .addr = 0xffda0000 + (_id * 0x1000), \
356 .dcr = HPB_DMAE_DCR_CT | \
357 HPB_DMAE_DCR_DIP | \
358 HPB_DMAE_DCR_SMDL | \
359 HPB_DMAE_DCR_SPDS_32BIT | \
360 HPB_DMAE_DCR_DPDS_32BIT, \
361 .port = 0x1111, \
362 .dma_ch = (28 + _id), \
363 }
364
365 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
366 {
367 .id = HPBDMA_SLAVE_SDHI0_TX,
368 .addr = 0xffe4c000 + 0x30,
369 .dcr = HPB_DMAE_DCR_SPDS_16BIT |
370 HPB_DMAE_DCR_DMDL |
371 HPB_DMAE_DCR_DPDS_16BIT,
372 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
373 HPB_DMAE_ASYNCRSTR_ASRST22 |
374 HPB_DMAE_ASYNCRSTR_ASRST23,
375 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
376 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
377 .port = 0x0D0C,
378 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
379 .dma_ch = 21,
380 }, {
381 .id = HPBDMA_SLAVE_SDHI0_RX,
382 .addr = 0xffe4c000 + 0x30,
383 .dcr = HPB_DMAE_DCR_SMDL |
384 HPB_DMAE_DCR_SPDS_16BIT |
385 HPB_DMAE_DCR_DPDS_16BIT,
386 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
387 HPB_DMAE_ASYNCRSTR_ASRST22 |
388 HPB_DMAE_ASYNCRSTR_ASRST23,
389 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
390 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
391 .port = 0x0D0C,
392 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
393 .dma_ch = 22,
394 }, {
395 .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
396 .addr = 0xffe60018,
397 .dcr = HPB_DMAE_DCR_SPDS_32BIT |
398 HPB_DMAE_DCR_DMDL |
399 HPB_DMAE_DCR_DPDS_32BIT,
400 .port = 0x0000,
401 .dma_ch = 14,
402 }, {
403 .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
404 .addr = 0xffe6001c,
405 .dcr = HPB_DMAE_DCR_SMDL |
406 HPB_DMAE_DCR_SPDS_32BIT |
407 HPB_DMAE_DCR_DPDS_32BIT,
408 .port = 0x0101,
409 .dma_ch = 15,
410 },
411
412 HPBDMA_SSI(0),
413 HPBDMA_SSI(1),
414 HPBDMA_SSI(2),
415 HPBDMA_SSI(3),
416 HPBDMA_SSI(4),
417 HPBDMA_SSI(5),
418 HPBDMA_SSI(6),
419 HPBDMA_SSI(7),
420 HPBDMA_SSI(8),
421
422 HPBDMA_HPBIF(0),
423 HPBDMA_HPBIF(1),
424 HPBDMA_HPBIF(2),
425 HPBDMA_HPBIF(3),
426 HPBDMA_HPBIF(4),
427 HPBDMA_HPBIF(5),
428 HPBDMA_HPBIF(6),
429 HPBDMA_HPBIF(7),
430 HPBDMA_HPBIF(8),
431 };
432
433 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
434 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
435 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
436 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
437 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
438 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
439 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
440 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
441 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
442 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
443 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
444 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
445 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
446 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
447 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
458 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
459 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
460 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
461 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
462 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
463 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
464 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
465 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
466 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
467 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
468 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
469 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
470 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
471 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
472 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
473 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
474 };
475
476 static struct hpb_dmae_pdata dma_platform_data __initdata = {
477 .slaves = hpb_dmae_slaves,
478 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
479 .channels = hpb_dmae_channels,
480 .num_channels = ARRAY_SIZE(hpb_dmae_channels),
481 .ts_shift = {
482 [XMIT_SZ_8BIT] = 0,
483 [XMIT_SZ_16BIT] = 1,
484 [XMIT_SZ_32BIT] = 2,
485 },
486 .num_hw_channels = 39,
487 };
488
489 static struct resource hpb_dmae_resources[] __initdata = {
490 /* Channel registers */
491 DEFINE_RES_MEM(0xffc08000, 0x1000),
492 /* Common registers */
493 DEFINE_RES_MEM(0xffc09000, 0x170),
494 /* Asynchronous reset registers */
495 DEFINE_RES_MEM(0xffc00300, 4),
496 /* Asynchronous mode registers */
497 DEFINE_RES_MEM(0xffc00400, 4),
498 /* IRQ for DMA channels */
499 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
500 };
501
502 static void __init r8a7778_register_hpb_dmae(void)
503 {
504 platform_device_register_resndata(NULL, "hpb-dma-engine",
505 -1, hpb_dmae_resources,
506 ARRAY_SIZE(hpb_dmae_resources),
507 &dma_platform_data,
508 sizeof(dma_platform_data));
509 }
510
511 void __init r8a7778_add_standard_devices(void)
512 {
513 r8a7778_add_dt_devices();
514 r8a7778_register_tmu(0);
515 r8a7778_register_scif(0);
516 r8a7778_register_scif(1);
517 r8a7778_register_scif(2);
518 r8a7778_register_scif(3);
519 r8a7778_register_scif(4);
520 r8a7778_register_scif(5);
521 r8a7778_register_i2c(0);
522 r8a7778_register_i2c(1);
523 r8a7778_register_i2c(2);
524 r8a7778_register_i2c(3);
525 r8a7778_register_hspi(0);
526 r8a7778_register_hspi(1);
527 r8a7778_register_hspi(2);
528
529 r8a7778_register_hpb_dmae();
530 }
531
532 void __init r8a7778_init_late(void)
533 {
534 shmobile_init_late();
535 platform_device_register_full(&ehci_info);
536 platform_device_register_full(&ohci_info);
537 }
538
539 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
540 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
541 .sense_bitfield_width = 2,
542 };
543
544 static struct resource irqpin_resources[] __initdata = {
545 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
546 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
547 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
548 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
549 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
550 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
551 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
552 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
553 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
554 };
555
556 void __init r8a7778_init_irq_extpin_dt(int irlm)
557 {
558 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
559 unsigned long tmp;
560
561 if (!icr0) {
562 pr_warn("r8a7778: unable to setup external irq pin mode\n");
563 return;
564 }
565
566 tmp = ioread32(icr0);
567 if (irlm)
568 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
569 else
570 tmp &= ~(1 << 23); /* IRL mode - not supported */
571 tmp |= (1 << 21); /* LVLMODE = 1 */
572 iowrite32(tmp, icr0);
573 iounmap(icr0);
574 }
575
576 void __init r8a7778_init_irq_extpin(int irlm)
577 {
578 r8a7778_init_irq_extpin_dt(irlm);
579 if (irlm)
580 platform_device_register_resndata(
581 NULL, "renesas_intc_irqpin", -1,
582 irqpin_resources, ARRAY_SIZE(irqpin_resources),
583 &irqpin_platform_data, sizeof(irqpin_platform_data));
584 }
585
586 #ifdef CONFIG_USE_OF
587 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */
588 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */
589
590 #define INT2NTSR0 0x00018 /* 0xfe700018 */
591 #define INT2NTSR1 0x0002c /* 0xfe70002c */
592 void __init r8a7778_init_irq_dt(void)
593 {
594 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
595 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
596 void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
597 void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
598 #endif
599
600 BUG_ON(!base);
601
602 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
603 gic_init(0, 29, gic_dist_base, gic_cpu_base);
604 #else
605 irqchip_init();
606 #endif
607 /* route all interrupts to ARM */
608 __raw_writel(0x73ffffff, base + INT2NTSR0);
609 __raw_writel(0xffffffff, base + INT2NTSR1);
610
611 /* unmask all known interrupts in INTCS2 */
612 __raw_writel(0x08330773, base + INT2SMSKCR0);
613 __raw_writel(0x00311110, base + INT2SMSKCR1);
614
615 iounmap(base);
616 }
617
618 static const char *const r8a7778_compat_dt[] __initconst = {
619 "renesas,r8a7778",
620 NULL,
621 };
622
623 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
624 .init_early = shmobile_init_delay,
625 .init_irq = r8a7778_init_irq_dt,
626 .init_late = shmobile_init_late,
627 #ifdef CONFIG_COMMON_CLK
628 .init_time = r8a7778_timer_init,
629 #endif
630 .dt_compat = r8a7778_compat_dt,
631 MACHINE_END
632
633 #endif /* CONFIG_USE_OF */
CRIS linux kernel tree