arch/arm/mach-shmobile/setup-rcar-gen2.c

   1 /*
   2  * R-Car Generation 2 support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  * Copyright (C) 2014  Ulrich Hecht
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk/shmobile.h>
  19 #include <linux/clocksource.h>
  20 #include <linux/device.h>
  21 #include <linux/dma-contiguous.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/memblock.h>
  25 #include <linux/of.h>
  26 #include <linux/of_fdt.h>
  27 #include <asm/mach/arch.h>
  28 #include "common.h"
  29 #include "rcar-gen2.h"
  30
  31 #define MODEMR 0xe6160060
  32
  33 u32 rcar_gen2_read_mode_pins(void)
  34 {
  35         static u32 mode;
  36         static bool mode_valid;
  37
  38         if (!mode_valid) {
  39                 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
  40                 BUG_ON(!modemr);
  41                 mode = ioread32(modemr);
  42                 iounmap(modemr);
  43                 mode_valid = true;
  44         }
  45
  46         return mode;
  47 }
  48
  49 #define CNTCR 0
  50 #define CNTFID0 0x20
  51
  52 void __init rcar_gen2_timer_init(void)
  53 {
  54         u32 mode = rcar_gen2_read_mode_pins();
  55 #ifdef CONFIG_ARM_ARCH_TIMER
  56         void __iomem *base;
  57         int extal_mhz = 0;
  58         u32 freq;
  59
  60         if (of_machine_is_compatible("renesas,r8a7794")) {
  61                 freq = 260000000 / 8;   /* ZS / 8 */
  62                 /* CNTVOFF has to be initialized either from non-secure
  63                  * Hypervisor mode or secure Monitor mode with SCR.NS==1.
  64                  * If TrustZone is enabled then it should be handled by the
  65                  * secure code.
  66                  */
  67                 asm volatile(
  68                 "       cps     0x16\n"
  69                 "       mrc     p15, 0, r1, c1, c1, 0\n"
  70                 "       orr     r0, r1, #1\n"
  71                 "       mcr     p15, 0, r0, c1, c1, 0\n"
  72                 "       isb\n"
  73                 "       mov     r0, #0\n"
  74                 "       mcrr    p15, 4, r0, r0, c14\n"
  75                 "       isb\n"
  76                 "       mcr     p15, 0, r1, c1, c1, 0\n"
  77                 "       isb\n"
  78                 "       cps     0x13\n"
  79                         : : : "r0", "r1");
  80         } else {
  81                 /* At Linux boot time the r8a7790 arch timer comes up
  82                  * with the counter disabled. Moreover, it may also report
  83                  * a potentially incorrect fixed 13 MHz frequency. To be
  84                  * correct these registers need to be updated to use the
  85                  * frequency EXTAL / 2 which can be determined by the MD pins.
  86                  */
  87
  88                 switch (mode & (MD(14) | MD(13))) {
  89                 case 0:
  90                         extal_mhz = 15;
  91                         break;
  92                 case MD(13):
  93                         extal_mhz = 20;
  94                         break;
  95                 case MD(14):
  96                         extal_mhz = 26;
  97                         break;
  98                 case MD(13) | MD(14):
  99                         extal_mhz = 30;
 100                         break;
 101                 }
 102
 103                 /* The arch timer frequency equals EXTAL / 2 */
 104                 freq = extal_mhz * (1000000 / 2);
 105         }
 106
 107         /* Remap "armgcnt address map" space */
 108         base = ioremap(0xe6080000, PAGE_SIZE);
 109
 110         /*
 111          * Update the timer if it is either not running, or is not at the
 112          * right frequency. The timer is only configurable in secure mode
 113          * so this avoids an abort if the loader started the timer and
 114          * entered the kernel in non-secure mode.
 115          */
 116
 117         if ((ioread32(base + CNTCR) & 1) == 0 ||
 118             ioread32(base + CNTFID0) != freq) {
 119                 /* Update registers with correct frequency */
 120                 iowrite32(freq, base + CNTFID0);
 121                 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 122
 123                 /* make sure arch timer is started by setting bit 0 of CNTCR */
 124                 iowrite32(1, base + CNTCR);
 125         }
 126
 127         iounmap(base);
 128 #endif /* CONFIG_ARM_ARCH_TIMER */
 129
 130         rcar_gen2_clocks_init(mode);
 131         clocksource_of_init();
 132 }
 133
 134 struct memory_reserve_config {
 135         u64 reserved;
 136         u64 base, size;
 137 };
 138
 139 static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
 140                                      int depth, void *data)
 141 {
 142         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 143         const __be32 *reg, *endp;
 144         int l;
 145         struct memory_reserve_config *mrc = data;
 146         u64 lpae_start = 1ULL << 32;
 147
 148         /* We are scanning "memory" nodes only */
 149         if (type == NULL || strcmp(type, "memory"))
 150                 return 0;
 151
 152         reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
 153         if (reg == NULL)
 154                 reg = of_get_flat_dt_prop(node, "reg", &l);
 155         if (reg == NULL)
 156                 return 0;
 157
 158         endp = reg + (l / sizeof(__be32));
 159         while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
 160                 u64 base, size;
 161
 162                 base = dt_mem_next_cell(dt_root_addr_cells, &reg);
 163                 size = dt_mem_next_cell(dt_root_size_cells, &reg);
 164
 165                 if (base >= lpae_start)
 166                         continue;
 167
 168                 if ((base + size) >= lpae_start)
 169                         size = lpae_start - base;
 170
 171                 if (size < mrc->reserved)
 172                         continue;
 173
 174                 if (base < mrc->base)
 175                         continue;
 176
 177                 /* keep the area at top near the 32-bit legacy limit */
 178                 mrc->base = base + size - mrc->reserved;
 179                 mrc->size = mrc->reserved;
 180         }
 181
 182         return 0;
 183 }
 184
 185 struct cma *rcar_gen2_dma_contiguous;
 186
 187 void __init rcar_gen2_reserve(void)
 188 {
 189         struct memory_reserve_config mrc;
 190
 191         /* reserve 256 MiB at the top of the physical legacy 32-bit space */
 192         memset(&mrc, 0, sizeof(mrc));
 193         mrc.reserved = SZ_256M;
 194
 195         of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
 196 #ifdef CONFIG_DMA_CMA
 197         if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size))
 198                 dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
 199                                             &rcar_gen2_dma_contiguous, true);
 200 #endif
 201 }