arch/arm/plat-orion/gpio.c

   1 /*
   2  * arch/arm/plat-orion/gpio.c
   3  *
   4  * Marvell Orion SoC GPIO handling.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #define DEBUG
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/module.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/bitops.h>
  20 #include <linux/io.h>
  21 #include <linux/gpio.h>
  22 #include <linux/leds.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_address.h>
  26 #include <plat/orion-gpio.h>
  27
  28 /*
  29  * GPIO unit register offsets.
  30  */
  31 #define GPIO_OUT_OFF            0x0000
  32 #define GPIO_IO_CONF_OFF        0x0004
  33 #define GPIO_BLINK_EN_OFF       0x0008
  34 #define GPIO_IN_POL_OFF         0x000c
  35 #define GPIO_DATA_IN_OFF        0x0010
  36 #define GPIO_EDGE_CAUSE_OFF     0x0014
  37 #define GPIO_EDGE_MASK_OFF      0x0018
  38 #define GPIO_LEVEL_MASK_OFF     0x001c
  39
  40 struct orion_gpio_chip {
  41         struct gpio_chip        chip;
  42         spinlock_t              lock;
  43         void __iomem            *base;
  44         unsigned long           valid_input;
  45         unsigned long           valid_output;
  46         int                     mask_offset;
  47         int                     secondary_irq_base;
  48         struct irq_domain       *domain;
  49 };
  50
  51 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
  52 {
  53         return ochip->base + GPIO_OUT_OFF;
  54 }
  55
  56 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
  57 {
  58         return ochip->base + GPIO_IO_CONF_OFF;
  59 }
  60
  61 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
  62 {
  63         return ochip->base + GPIO_BLINK_EN_OFF;
  64 }
  65
  66 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
  67 {
  68         return ochip->base + GPIO_IN_POL_OFF;
  69 }
  70
  71 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
  72 {
  73         return ochip->base + GPIO_DATA_IN_OFF;
  74 }
  75
  76 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
  77 {
  78         return ochip->base + GPIO_EDGE_CAUSE_OFF;
  79 }
  80
  81 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
  82 {
  83         return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
  84 }
  85
  86 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
  87 {
  88         return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
  89 }
  90
  91
  92 static struct orion_gpio_chip orion_gpio_chips[2];
  93 static int orion_gpio_chip_count;
  94
  95 static inline void
  96 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
  97 {
  98         u32 u;
  99
 100         u = readl(GPIO_IO_CONF(ochip));
 101         if (input)
 102                 u |= 1 << pin;
 103         else
 104                 u &= ~(1 << pin);
 105         writel(u, GPIO_IO_CONF(ochip));
 106 }
 107
 108 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
 109 {
 110         u32 u;
 111
 112         u = readl(GPIO_OUT(ochip));
 113         if (high)
 114                 u |= 1 << pin;
 115         else
 116                 u &= ~(1 << pin);
 117         writel(u, GPIO_OUT(ochip));
 118 }
 119
 120 static inline void
 121 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
 122 {
 123         u32 u;
 124
 125         u = readl(GPIO_BLINK_EN(ochip));
 126         if (blink)
 127                 u |= 1 << pin;
 128         else
 129                 u &= ~(1 << pin);
 130         writel(u, GPIO_BLINK_EN(ochip));
 131 }
 132
 133 static inline int
 134 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
 135 {
 136         if (pin >= ochip->chip.ngpio)
 137                 goto err_out;
 138
 139         if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
 140                 goto err_out;
 141
 142         if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
 143                 goto err_out;
 144
 145         return 1;
 146
 147 err_out:
 148         pr_debug("%s: invalid GPIO %d\n", __func__, pin);
 149         return false;
 150 }
 151
 152 /*
 153  * GPIO primitives.
 154  */
 155 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
 156 {
 157         struct orion_gpio_chip *ochip =
 158                 container_of(chip, struct orion_gpio_chip, chip);
 159
 160         if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
 161             orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
 162                 return 0;
 163
 164         return -EINVAL;
 165 }
 166
 167 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 168 {
 169         struct orion_gpio_chip *ochip =
 170                 container_of(chip, struct orion_gpio_chip, chip);
 171         unsigned long flags;
 172
 173         if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
 174                 return -EINVAL;
 175
 176         spin_lock_irqsave(&ochip->lock, flags);
 177         __set_direction(ochip, pin, 1);
 178         spin_unlock_irqrestore(&ochip->lock, flags);
 179
 180         return 0;
 181 }
 182
 183 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
 184 {
 185         struct orion_gpio_chip *ochip =
 186                 container_of(chip, struct orion_gpio_chip, chip);
 187         int val;
 188
 189         if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
 190                 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
 191         } else {
 192                 val = readl(GPIO_OUT(ochip));
 193         }
 194
 195         return (val >> pin) & 1;
 196 }
 197
 198 static int
 199 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
 200 {
 201         struct orion_gpio_chip *ochip =
 202                 container_of(chip, struct orion_gpio_chip, chip);
 203         unsigned long flags;
 204
 205         if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
 206                 return -EINVAL;
 207
 208         spin_lock_irqsave(&ochip->lock, flags);
 209         __set_blinking(ochip, pin, 0);
 210         __set_level(ochip, pin, value);
 211         __set_direction(ochip, pin, 0);
 212         spin_unlock_irqrestore(&ochip->lock, flags);
 213
 214         return 0;
 215 }
 216
 217 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
 218 {
 219         struct orion_gpio_chip *ochip =
 220                 container_of(chip, struct orion_gpio_chip, chip);
 221         unsigned long flags;
 222
 223         spin_lock_irqsave(&ochip->lock, flags);
 224         __set_level(ochip, pin, value);
 225         spin_unlock_irqrestore(&ochip->lock, flags);
 226 }
 227
 228 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 229 {
 230         struct orion_gpio_chip *ochip =
 231                 container_of(chip, struct orion_gpio_chip, chip);
 232
 233         return irq_create_mapping(ochip->domain,
 234                                   ochip->secondary_irq_base + pin);
 235 }
 236
 237 /*
 238  * Orion-specific GPIO API extensions.
 239  */
 240 static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
 241 {
 242         int i;
 243
 244         for (i = 0; i < orion_gpio_chip_count; i++) {
 245                 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
 246                 struct gpio_chip *chip = &ochip->chip;
 247
 248                 if (pin >= chip->base && pin < chip->base + chip->ngpio)
 249                         return ochip;
 250         }
 251
 252         return NULL;
 253 }
 254
 255 void __init orion_gpio_set_unused(unsigned pin)
 256 {
 257         struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
 258
 259         if (ochip == NULL)
 260                 return;
 261
 262         pin -= ochip->chip.base;
 263
 264         /* Configure as output, drive low. */
 265         __set_level(ochip, pin, 0);
 266         __set_direction(ochip, pin, 0);
 267 }
 268
 269 void __init orion_gpio_set_valid(unsigned pin, int mode)
 270 {
 271         struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
 272
 273         if (ochip == NULL)
 274                 return;
 275
 276         pin -= ochip->chip.base;
 277
 278         if (mode == 1)
 279                 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
 280
 281         if (mode & GPIO_INPUT_OK)
 282                 __set_bit(pin, &ochip->valid_input);
 283         else
 284                 __clear_bit(pin, &ochip->valid_input);
 285
 286         if (mode & GPIO_OUTPUT_OK)
 287                 __set_bit(pin, &ochip->valid_output);
 288         else
 289                 __clear_bit(pin, &ochip->valid_output);
 290 }
 291
 292 void orion_gpio_set_blink(unsigned pin, int blink)
 293 {
 294         struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
 295         unsigned long flags;
 296
 297         if (ochip == NULL)
 298                 return;
 299
 300         spin_lock_irqsave(&ochip->lock, flags);
 301         __set_level(ochip, pin & 31, 0);
 302         __set_blinking(ochip, pin & 31, blink);
 303         spin_unlock_irqrestore(&ochip->lock, flags);
 304 }
 305 EXPORT_SYMBOL(orion_gpio_set_blink);
 306
 307 #define ORION_BLINK_HALF_PERIOD 100 /* ms */
 308
 309 int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
 310         unsigned long *delay_on, unsigned long *delay_off)
 311 {
 312         unsigned gpio = desc_to_gpio(desc);
 313
 314         if (delay_on && delay_off && !*delay_on && !*delay_off)
 315                 *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
 316
 317         switch (state) {
 318         case GPIO_LED_NO_BLINK_LOW:
 319         case GPIO_LED_NO_BLINK_HIGH:
 320                 orion_gpio_set_blink(gpio, 0);
 321                 gpio_set_value(gpio, state);
 322                 break;
 323         case GPIO_LED_BLINK:
 324                 orion_gpio_set_blink(gpio, 1);
 325         }
 326         return 0;
 327 }
 328 EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
 329
 330
 331 /*****************************************************************************
 332  * Orion GPIO IRQ
 333  *
 334  * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 335  * value of the line or the opposite value.
 336  *
 337  * Level IRQ handlers: DATA_IN is used directly as cause register.
 338  *                     Interrupt are masked by LEVEL_MASK registers.
 339  * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 340  *                     Interrupt are masked by EDGE_MASK registers.
 341  * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 342  *                     the polarity to catch the next line transaction.
 343  *                     This is a race condition that might not perfectly
 344  *                     work on some use cases.
 345  *
 346  * Every eight GPIO lines are grouped (OR'ed) before going up to main
 347  * cause register.
 348  *
 349  *                    EDGE  cause    mask
 350  *        data-in   /--------| |-----| |----\
 351  *     -----| |-----                         ---- to main cause reg
 352  *           X      \----------------| |----/
 353  *        polarity    LEVEL          mask
 354  *
 355  ****************************************************************************/
 356
 357 static int gpio_irq_set_type(struct irq_data *d, u32 type)
 358 {
 359         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 360         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 361         struct orion_gpio_chip *ochip = gc->private;
 362         int pin;
 363         u32 u;
 364
 365         pin = d->hwirq - ochip->secondary_irq_base;
 366
 367         u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
 368         if (!u) {
 369                 return -EINVAL;
 370         }
 371
 372         type &= IRQ_TYPE_SENSE_MASK;
 373         if (type == IRQ_TYPE_NONE)
 374                 return -EINVAL;
 375
 376         /* Check if we need to change chip and handler */
 377         if (!(ct->type & type))
 378                 if (irq_setup_alt_chip(d, type))
 379                         return -EINVAL;
 380
 381         /*
 382          * Configure interrupt polarity.
 383          */
 384         if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
 385                 u = readl(GPIO_IN_POL(ochip));
 386                 u &= ~(1 << pin);
 387                 writel(u, GPIO_IN_POL(ochip));
 388         } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
 389                 u = readl(GPIO_IN_POL(ochip));
 390                 u |= 1 << pin;
 391                 writel(u, GPIO_IN_POL(ochip));
 392         } else if (type == IRQ_TYPE_EDGE_BOTH) {
 393                 u32 v;
 394
 395                 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
 396
 397                 /*
 398                  * set initial polarity based on current input level
 399                  */
 400                 u = readl(GPIO_IN_POL(ochip));
 401                 if (v & (1 << pin))
 402                         u |= 1 << pin;          /* falling */
 403                 else
 404                         u &= ~(1 << pin);       /* rising */
 405                 writel(u, GPIO_IN_POL(ochip));
 406         }
 407         return 0;
 408 }
 409
 410 static void gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
 411 {
 412         struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
 413         u32 cause, type;
 414         int i;
 415
 416         if (ochip == NULL)
 417                 return;
 418
 419         cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
 420         cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
 421
 422         for (i = 0; i < ochip->chip.ngpio; i++) {
 423                 int irq;
 424
 425                 irq = ochip->secondary_irq_base + i;
 426
 427                 if (!(cause & (1 << i)))
 428                         continue;
 429
 430                 type = irq_get_trigger_type(irq);
 431                 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 432                         /* Swap polarity (race with GPIO line) */
 433                         u32 polarity;
 434
 435                         polarity = readl(GPIO_IN_POL(ochip));
 436                         polarity ^= 1 << i;
 437                         writel(polarity, GPIO_IN_POL(ochip));
 438                 }
 439                 generic_handle_irq(irq);
 440         }
 441 }
 442
 443 #ifdef CONFIG_DEBUG_FS
 444 #include <linux/seq_file.h>
 445
 446 static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 447 {
 448         struct orion_gpio_chip *ochip =
 449                 container_of(chip, struct orion_gpio_chip, chip);
 450         u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
 451         int i;
 452
 453         out     = readl_relaxed(GPIO_OUT(ochip));
 454         io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
 455         blink   = readl_relaxed(GPIO_BLINK_EN(ochip));
 456         in_pol  = readl_relaxed(GPIO_IN_POL(ochip));
 457         data_in = readl_relaxed(GPIO_DATA_IN(ochip));
 458         cause   = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
 459         edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
 460         lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
 461
 462         for (i = 0; i < chip->ngpio; i++) {
 463                 const char *label;
 464                 u32 msk;
 465                 bool is_out;
 466
 467                 label = gpiochip_is_requested(chip, i);
 468                 if (!label)
 469                         continue;
 470
 471                 msk = 1 << i;
 472                 is_out = !(io_conf & msk);
 473
 474                 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
 475
 476                 if (is_out) {
 477                         seq_printf(s, " out %s %s\n",
 478                                    out & msk ? "hi" : "lo",
 479                                    blink & msk ? "(blink )" : "");
 480                         continue;
 481                 }
 482
 483                 seq_printf(s, " in  %s (act %s) - IRQ",
 484                            (data_in ^ in_pol) & msk  ? "hi" : "lo",
 485                            in_pol & msk ? "lo" : "hi");
 486                 if (!((edg_msk | lvl_msk) & msk)) {
 487                         seq_printf(s, " disabled\n");
 488                         continue;
 489                 }
 490                 if (edg_msk & msk)
 491                         seq_printf(s, " edge ");
 492                 if (lvl_msk & msk)
 493                         seq_printf(s, " level");
 494                 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
 495         }
 496 }
 497 #else
 498 #define orion_gpio_dbg_show NULL
 499 #endif
 500
 501 static void orion_gpio_unmask_irq(struct irq_data *d)
 502 {
 503         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 504         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 505         u32 reg_val;
 506         u32 mask = d->mask;
 507
 508         irq_gc_lock(gc);
 509         reg_val = irq_reg_readl(gc, ct->regs.mask);
 510         reg_val |= mask;
 511         irq_reg_writel(gc, reg_val, ct->regs.mask);
 512         irq_gc_unlock(gc);
 513 }
 514
 515 static void orion_gpio_mask_irq(struct irq_data *d)
 516 {
 517         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 518         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 519         u32 mask = d->mask;
 520         u32 reg_val;
 521
 522         irq_gc_lock(gc);
 523         reg_val = irq_reg_readl(gc, ct->regs.mask);
 524         reg_val &= ~mask;
 525         irq_reg_writel(gc, reg_val, ct->regs.mask);
 526         irq_gc_unlock(gc);
 527 }
 528
 529 void __init orion_gpio_init(struct device_node *np,
 530                             int gpio_base, int ngpio,
 531                             void __iomem *base, int mask_offset,
 532                             int secondary_irq_base,
 533                             int irqs[4])
 534 {
 535         struct orion_gpio_chip *ochip;
 536         struct irq_chip_generic *gc;
 537         struct irq_chip_type *ct;
 538         char gc_label[16];
 539         int i;
 540
 541         if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
 542                 return;
 543
 544         snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
 545                 orion_gpio_chip_count);
 546
 547         ochip = orion_gpio_chips + orion_gpio_chip_count;
 548         ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
 549         ochip->chip.request = orion_gpio_request;
 550         ochip->chip.direction_input = orion_gpio_direction_input;
 551         ochip->chip.get = orion_gpio_get;
 552         ochip->chip.direction_output = orion_gpio_direction_output;
 553         ochip->chip.set = orion_gpio_set;
 554         ochip->chip.to_irq = orion_gpio_to_irq;
 555         ochip->chip.base = gpio_base;
 556         ochip->chip.ngpio = ngpio;
 557         ochip->chip.can_sleep = 0;
 558 #ifdef CONFIG_OF
 559         ochip->chip.of_node = np;
 560 #endif
 561         ochip->chip.dbg_show = orion_gpio_dbg_show;
 562
 563         spin_lock_init(&ochip->lock);
 564         ochip->base = (void __iomem *)base;
 565         ochip->valid_input = 0;
 566         ochip->valid_output = 0;
 567         ochip->mask_offset = mask_offset;
 568         ochip->secondary_irq_base = secondary_irq_base;
 569
 570         gpiochip_add(&ochip->chip);
 571
 572         /*
 573          * Mask and clear GPIO interrupts.
 574          */
 575         writel(0, GPIO_EDGE_CAUSE(ochip));
 576         writel(0, GPIO_EDGE_MASK(ochip));
 577         writel(0, GPIO_LEVEL_MASK(ochip));
 578
 579         /* Setup the interrupt handlers. Each chip can have up to 4
 580          * interrupt handlers, with each handler dealing with 8 GPIO
 581          * pins. */
 582
 583         for (i = 0; i < 4; i++) {
 584                 if (irqs[i]) {
 585                         irq_set_chained_handler_and_data(irqs[i],
 586                                                          gpio_irq_handler,
 587                                                          ochip);
 588                 }
 589         }
 590
 591         gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
 592                                     secondary_irq_base,
 593                                     ochip->base, handle_level_irq);
 594         gc->private = ochip;
 595         ct = gc->chip_types;
 596         ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
 597         ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
 598         ct->chip.irq_mask = orion_gpio_mask_irq;
 599         ct->chip.irq_unmask = orion_gpio_unmask_irq;
 600         ct->chip.irq_set_type = gpio_irq_set_type;
 601         ct->chip.name = ochip->chip.label;
 602
 603         ct++;
 604         ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
 605         ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
 606         ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 607         ct->chip.irq_ack = irq_gc_ack_clr_bit;
 608         ct->chip.irq_mask = orion_gpio_mask_irq;
 609         ct->chip.irq_unmask = orion_gpio_unmask_irq;
 610         ct->chip.irq_set_type = gpio_irq_set_type;
 611         ct->handler = handle_edge_irq;
 612         ct->chip.name = ochip->chip.label;
 613
 614         irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
 615                                IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 616
 617         /* Setup irq domain on top of the generic chip. */
 618         ochip->domain = irq_domain_add_legacy(np,
 619                                               ochip->chip.ngpio,
 620                                               ochip->secondary_irq_base,
 621                                               ochip->secondary_irq_base,
 622                                               &irq_domain_simple_ops,
 623                                               ochip);
 624         if (!ochip->domain)
 625                 panic("%s: couldn't allocate irq domain (DT).\n",
 626                       ochip->chip.label);
 627
 628         orion_gpio_chip_count++;
 629 }