arch/powerpc/kernel/sysfs.c

   1 #include <linux/device.h>
   2 #include <linux/cpu.h>
   3 #include <linux/smp.h>
   4 #include <linux/percpu.h>
   5 #include <linux/init.h>
   6 #include <linux/sched.h>
   7 #include <linux/export.h>
   8 #include <linux/nodemask.h>
   9 #include <linux/cpumask.h>
  10 #include <linux/notifier.h>
  11
  12 #include <asm/current.h>
  13 #include <asm/processor.h>
  14 #include <asm/cputable.h>
  15 #include <asm/hvcall.h>
  16 #include <asm/prom.h>
  17 #include <asm/machdep.h>
  18 #include <asm/smp.h>
  19 #include <asm/pmc.h>
  20 #include <asm/firmware.h>
  21
  22 #include "cacheinfo.h"
  23
  24 #ifdef CONFIG_PPC64
  25 #include <asm/paca.h>
  26 #include <asm/lppaca.h>
  27 #endif
  28
  29 static DEFINE_PER_CPU(struct cpu, cpu_devices);
  30
  31 /*
  32  * SMT snooze delay stuff, 64-bit only for now
  33  */
  34
  35 #ifdef CONFIG_PPC64
  36
  37 /* Time in microseconds we delay before sleeping in the idle loop */
  38 DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
  39
  40 static ssize_t store_smt_snooze_delay(struct device *dev,
  41                                       struct device_attribute *attr,
  42                                       const char *buf,
  43                                       size_t count)
  44 {
  45         struct cpu *cpu = container_of(dev, struct cpu, dev);
  46         ssize_t ret;
  47         long snooze;
  48
  49         ret = sscanf(buf, "%ld", &snooze);
  50         if (ret != 1)
  51                 return -EINVAL;
  52
  53         per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
  54         return count;
  55 }
  56
  57 static ssize_t show_smt_snooze_delay(struct device *dev,
  58                                      struct device_attribute *attr,
  59                                      char *buf)
  60 {
  61         struct cpu *cpu = container_of(dev, struct cpu, dev);
  62
  63         return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
  64 }
  65
  66 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
  67                    store_smt_snooze_delay);
  68
  69 static int __init setup_smt_snooze_delay(char *str)
  70 {
  71         unsigned int cpu;
  72         long snooze;
  73
  74         if (!cpu_has_feature(CPU_FTR_SMT))
  75                 return 1;
  76
  77         snooze = simple_strtol(str, NULL, 10);
  78         for_each_possible_cpu(cpu)
  79                 per_cpu(smt_snooze_delay, cpu) = snooze;
  80
  81         return 1;
  82 }
  83 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
  84
  85 #endif /* CONFIG_PPC64 */
  86
  87 #ifdef CONFIG_PPC_FSL_BOOK3E
  88 #define MAX_BIT                         63
  89
  90 static u64 pw20_wt;
  91 static u64 altivec_idle_wt;
  92
  93 static unsigned int get_idle_ticks_bit(u64 ns)
  94 {
  95         u64 cycle;
  96
  97         if (ns >= 10000)
  98                 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
  99         else
 100                 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
 101
 102         if (!cycle)
 103                 return 0;
 104
 105         return ilog2(cycle);
 106 }
 107
 108 static void do_show_pwrmgtcr0(void *val)
 109 {
 110         u32 *value = val;
 111
 112         *value = mfspr(SPRN_PWRMGTCR0);
 113 }
 114
 115 static ssize_t show_pw20_state(struct device *dev,
 116                                 struct device_attribute *attr, char *buf)
 117 {
 118         u32 value;
 119         unsigned int cpu = dev->id;
 120
 121         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 122
 123         value &= PWRMGTCR0_PW20_WAIT;
 124
 125         return sprintf(buf, "%u\n", value ? 1 : 0);
 126 }
 127
 128 static void do_store_pw20_state(void *val)
 129 {
 130         u32 *value = val;
 131         u32 pw20_state;
 132
 133         pw20_state = mfspr(SPRN_PWRMGTCR0);
 134
 135         if (*value)
 136                 pw20_state |= PWRMGTCR0_PW20_WAIT;
 137         else
 138                 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
 139
 140         mtspr(SPRN_PWRMGTCR0, pw20_state);
 141 }
 142
 143 static ssize_t store_pw20_state(struct device *dev,
 144                                 struct device_attribute *attr,
 145                                 const char *buf, size_t count)
 146 {
 147         u32 value;
 148         unsigned int cpu = dev->id;
 149
 150         if (kstrtou32(buf, 0, &value))
 151                 return -EINVAL;
 152
 153         if (value > 1)
 154                 return -EINVAL;
 155
 156         smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
 157
 158         return count;
 159 }
 160
 161 static ssize_t show_pw20_wait_time(struct device *dev,
 162                                 struct device_attribute *attr, char *buf)
 163 {
 164         u32 value;
 165         u64 tb_cycle = 1;
 166         u64 time;
 167
 168         unsigned int cpu = dev->id;
 169
 170         if (!pw20_wt) {
 171                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 172                 value = (value & PWRMGTCR0_PW20_ENT) >>
 173                                         PWRMGTCR0_PW20_ENT_SHIFT;
 174
 175                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 176                 /* convert ms to ns */
 177                 if (tb_ticks_per_usec > 1000) {
 178                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 179                 } else {
 180                         u32 rem_us;
 181
 182                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 183                                                 &rem_us);
 184                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 185                 }
 186         } else {
 187                 time = pw20_wt;
 188         }
 189
 190         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 191 }
 192
 193 static void set_pw20_wait_entry_bit(void *val)
 194 {
 195         u32 *value = val;
 196         u32 pw20_idle;
 197
 198         pw20_idle = mfspr(SPRN_PWRMGTCR0);
 199
 200         /* Set Automatic PW20 Core Idle Count */
 201         /* clear count */
 202         pw20_idle &= ~PWRMGTCR0_PW20_ENT;
 203
 204         /* set count */
 205         pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
 206
 207         mtspr(SPRN_PWRMGTCR0, pw20_idle);
 208 }
 209
 210 static ssize_t store_pw20_wait_time(struct device *dev,
 211                                 struct device_attribute *attr,
 212                                 const char *buf, size_t count)
 213 {
 214         u32 entry_bit;
 215         u64 value;
 216
 217         unsigned int cpu = dev->id;
 218
 219         if (kstrtou64(buf, 0, &value))
 220                 return -EINVAL;
 221
 222         if (!value)
 223                 return -EINVAL;
 224
 225         entry_bit = get_idle_ticks_bit(value);
 226         if (entry_bit > MAX_BIT)
 227                 return -EINVAL;
 228
 229         pw20_wt = value;
 230
 231         smp_call_function_single(cpu, set_pw20_wait_entry_bit,
 232                                 &entry_bit, 1);
 233
 234         return count;
 235 }
 236
 237 static ssize_t show_altivec_idle(struct device *dev,
 238                                 struct device_attribute *attr, char *buf)
 239 {
 240         u32 value;
 241         unsigned int cpu = dev->id;
 242
 243         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 244
 245         value &= PWRMGTCR0_AV_IDLE_PD_EN;
 246
 247         return sprintf(buf, "%u\n", value ? 1 : 0);
 248 }
 249
 250 static void do_store_altivec_idle(void *val)
 251 {
 252         u32 *value = val;
 253         u32 altivec_idle;
 254
 255         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 256
 257         if (*value)
 258                 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
 259         else
 260                 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
 261
 262         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 263 }
 264
 265 static ssize_t store_altivec_idle(struct device *dev,
 266                                 struct device_attribute *attr,
 267                                 const char *buf, size_t count)
 268 {
 269         u32 value;
 270         unsigned int cpu = dev->id;
 271
 272         if (kstrtou32(buf, 0, &value))
 273                 return -EINVAL;
 274
 275         if (value > 1)
 276                 return -EINVAL;
 277
 278         smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
 279
 280         return count;
 281 }
 282
 283 static ssize_t show_altivec_idle_wait_time(struct device *dev,
 284                                 struct device_attribute *attr, char *buf)
 285 {
 286         u32 value;
 287         u64 tb_cycle = 1;
 288         u64 time;
 289
 290         unsigned int cpu = dev->id;
 291
 292         if (!altivec_idle_wt) {
 293                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 294                 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
 295                                         PWRMGTCR0_AV_IDLE_CNT_SHIFT;
 296
 297                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 298                 /* convert ms to ns */
 299                 if (tb_ticks_per_usec > 1000) {
 300                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 301                 } else {
 302                         u32 rem_us;
 303
 304                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 305                                                 &rem_us);
 306                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 307                 }
 308         } else {
 309                 time = altivec_idle_wt;
 310         }
 311
 312         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 313 }
 314
 315 static void set_altivec_idle_wait_entry_bit(void *val)
 316 {
 317         u32 *value = val;
 318         u32 altivec_idle;
 319
 320         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 321
 322         /* Set Automatic AltiVec Idle Count */
 323         /* clear count */
 324         altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
 325
 326         /* set count */
 327         altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
 328
 329         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 330 }
 331
 332 static ssize_t store_altivec_idle_wait_time(struct device *dev,
 333                                 struct device_attribute *attr,
 334                                 const char *buf, size_t count)
 335 {
 336         u32 entry_bit;
 337         u64 value;
 338
 339         unsigned int cpu = dev->id;
 340
 341         if (kstrtou64(buf, 0, &value))
 342                 return -EINVAL;
 343
 344         if (!value)
 345                 return -EINVAL;
 346
 347         entry_bit = get_idle_ticks_bit(value);
 348         if (entry_bit > MAX_BIT)
 349                 return -EINVAL;
 350
 351         altivec_idle_wt = value;
 352
 353         smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
 354                                 &entry_bit, 1);
 355
 356         return count;
 357 }
 358
 359 /*
 360  * Enable/Disable interface:
 361  * 0, disable. 1, enable.
 362  */
 363 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
 364 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
 365
 366 /*
 367  * Set wait time interface:(Nanosecond)
 368  * Example: Base on TBfreq is 41MHZ.
 369  * 1~48(ns): TB[63]
 370  * 49~97(ns): TB[62]
 371  * 98~195(ns): TB[61]
 372  * 196~390(ns): TB[60]
 373  * 391~780(ns): TB[59]
 374  * 781~1560(ns): TB[58]
 375  * ...
 376  */
 377 static DEVICE_ATTR(pw20_wait_time, 0600,
 378                         show_pw20_wait_time,
 379                         store_pw20_wait_time);
 380 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
 381                         show_altivec_idle_wait_time,
 382                         store_altivec_idle_wait_time);
 383 #endif
 384
 385 /*
 386  * Enabling PMCs will slow partition context switch times so we only do
 387  * it the first time we write to the PMCs.
 388  */
 389
 390 static DEFINE_PER_CPU(char, pmcs_enabled);
 391
 392 void ppc_enable_pmcs(void)
 393 {
 394         ppc_set_pmu_inuse(1);
 395
 396         /* Only need to enable them once */
 397         if (__this_cpu_read(pmcs_enabled))
 398                 return;
 399
 400         __this_cpu_write(pmcs_enabled, 1);
 401
 402         if (ppc_md.enable_pmcs)
 403                 ppc_md.enable_pmcs();
 404 }
 405 EXPORT_SYMBOL(ppc_enable_pmcs);
 406
 407 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
 408 static void read_##NAME(void *val) \
 409 { \
 410         *(unsigned long *)val = mfspr(ADDRESS); \
 411 } \
 412 static void write_##NAME(void *val) \
 413 { \
 414         EXTRA; \
 415         mtspr(ADDRESS, *(unsigned long *)val);  \
 416 }
 417
 418 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 419 static ssize_t show_##NAME(struct device *dev, \
 420                         struct device_attribute *attr, \
 421                         char *buf) \
 422 { \
 423         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 424         unsigned long val; \
 425         smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
 426         return sprintf(buf, "%lx\n", val); \
 427 } \
 428 static ssize_t __used \
 429         store_##NAME(struct device *dev, struct device_attribute *attr, \
 430                         const char *buf, size_t count) \
 431 { \
 432         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 433         unsigned long val; \
 434         int ret = sscanf(buf, "%lx", &val); \
 435         if (ret != 1) \
 436                 return -EINVAL; \
 437         smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
 438         return count; \
 439 }
 440
 441 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
 442         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
 443         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 444 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
 445         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
 446         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 447
 448 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 449         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 450
 451 /* Let's define all possible registers, we'll only hook up the ones
 452  * that are implemented on the current processor
 453  */
 454
 455 #if defined(CONFIG_PPC64)
 456 #define HAS_PPC_PMC_CLASSIC     1
 457 #define HAS_PPC_PMC_IBM         1
 458 #define HAS_PPC_PMC_PA6T        1
 459 #elif defined(CONFIG_6xx)
 460 #define HAS_PPC_PMC_CLASSIC     1
 461 #define HAS_PPC_PMC_IBM         1
 462 #define HAS_PPC_PMC_G4          1
 463 #endif
 464
 465
 466 #ifdef HAS_PPC_PMC_CLASSIC
 467 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
 468 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
 469 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
 470 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
 471 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
 472 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
 473 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
 474 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
 475
 476 #ifdef HAS_PPC_PMC_G4
 477 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
 478 #endif
 479
 480 #ifdef CONFIG_PPC64
 481 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 482 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 483
 484 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 485 SYSFS_SPRSETUP(purr, SPRN_PURR);
 486 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
 487 SYSFS_SPRSETUP(pir, SPRN_PIR);
 488
 489 /*
 490   Lets only enable read for phyp resources and
 491   enable write when needed with a separate function.
 492   Lets be conservative and default to pseries.
 493 */
 494 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 495 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 496 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 497 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 498
 499 /*
 500  * This is the system wide DSCR register default value. Any
 501  * change to this default value through the sysfs interface
 502  * will update all per cpu DSCR default values across the
 503  * system stored in their respective PACA structures.
 504  */
 505 static unsigned long dscr_default;
 506
 507 /**
 508  * read_dscr() - Fetch the cpu specific DSCR default
 509  * @val:        Returned cpu specific DSCR default value
 510  *
 511  * This function returns the per cpu DSCR default value
 512  * for any cpu which is contained in it's PACA structure.
 513  */
 514 static void read_dscr(void *val)
 515 {
 516         *(unsigned long *)val = get_paca()->dscr_default;
 517 }
 518
 519
 520 /**
 521  * write_dscr() - Update the cpu specific DSCR default
 522  * @val:        New cpu specific DSCR default value to update
 523  *
 524  * This function updates the per cpu DSCR default value
 525  * for any cpu which is contained in it's PACA structure.
 526  */
 527 static void write_dscr(void *val)
 528 {
 529         get_paca()->dscr_default = *(unsigned long *)val;
 530         if (!current->thread.dscr_inherit) {
 531                 current->thread.dscr = *(unsigned long *)val;
 532                 mtspr(SPRN_DSCR, *(unsigned long *)val);
 533         }
 534 }
 535
 536 SYSFS_SPRSETUP_SHOW_STORE(dscr);
 537 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 538
 539 static void add_write_permission_dev_attr(struct device_attribute *attr)
 540 {
 541         attr->attr.mode |= 0200;
 542 }
 543
 544 /**
 545  * show_dscr_default() - Fetch the system wide DSCR default
 546  * @dev:        Device structure
 547  * @attr:       Device attribute structure
 548  * @buf:        Interface buffer
 549  *
 550  * This function returns the system wide DSCR default value.
 551  */
 552 static ssize_t show_dscr_default(struct device *dev,
 553                 struct device_attribute *attr, char *buf)
 554 {
 555         return sprintf(buf, "%lx\n", dscr_default);
 556 }
 557
 558 /**
 559  * store_dscr_default() - Update the system wide DSCR default
 560  * @dev:        Device structure
 561  * @attr:       Device attribute structure
 562  * @buf:        Interface buffer
 563  * @count:      Size of the update
 564  *
 565  * This function updates the system wide DSCR default value.
 566  */
 567 static ssize_t __used store_dscr_default(struct device *dev,
 568                 struct device_attribute *attr, const char *buf,
 569                 size_t count)
 570 {
 571         unsigned long val;
 572         int ret = 0;
 573
 574         ret = sscanf(buf, "%lx", &val);
 575         if (ret != 1)
 576                 return -EINVAL;
 577         dscr_default = val;
 578
 579         on_each_cpu(write_dscr, &val, 1);
 580
 581         return count;
 582 }
 583
 584 static DEVICE_ATTR(dscr_default, 0600,
 585                 show_dscr_default, store_dscr_default);
 586
 587 static void sysfs_create_dscr_default(void)
 588 {
 589         int err = 0;
 590         if (cpu_has_feature(CPU_FTR_DSCR))
 591                 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
 592 }
 593 #endif /* CONFIG_PPC64 */
 594
 595 #ifdef HAS_PPC_PMC_PA6T
 596 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
 597 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
 598 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
 599 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 600 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 601 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 602 #ifdef CONFIG_DEBUG_KERNEL
 603 SYSFS_SPRSETUP(hid0, SPRN_HID0);
 604 SYSFS_SPRSETUP(hid1, SPRN_HID1);
 605 SYSFS_SPRSETUP(hid4, SPRN_HID4);
 606 SYSFS_SPRSETUP(hid5, SPRN_HID5);
 607 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
 608 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
 609 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
 610 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
 611 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
 612 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
 613 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
 614 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
 615 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
 616 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
 617 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
 618 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
 619 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
 620 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
 621 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
 622 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
 623 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
 624 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
 625 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
 626 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
 627 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
 628 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
 629 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
 630 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 631 #endif /* CONFIG_DEBUG_KERNEL */
 632 #endif /* HAS_PPC_PMC_PA6T */
 633
 634 #ifdef HAS_PPC_PMC_IBM
 635 static struct device_attribute ibm_common_attrs[] = {
 636         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 637         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 638 };
 639 #endif /* HAS_PPC_PMC_G4 */
 640
 641 #ifdef HAS_PPC_PMC_G4
 642 static struct device_attribute g4_common_attrs[] = {
 643         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 644         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 645         __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
 646 };
 647 #endif /* HAS_PPC_PMC_G4 */
 648
 649 static struct device_attribute classic_pmc_attrs[] = {
 650         __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
 651         __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
 652         __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
 653         __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
 654         __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
 655         __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
 656 #ifdef CONFIG_PPC64
 657         __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
 658         __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
 659 #endif
 660 };
 661
 662 #ifdef HAS_PPC_PMC_PA6T
 663 static struct device_attribute pa6t_attrs[] = {
 664         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 665         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 666         __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
 667         __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
 668         __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
 669         __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
 670         __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
 671         __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
 672 #ifdef CONFIG_DEBUG_KERNEL
 673         __ATTR(hid0, 0600, show_hid0, store_hid0),
 674         __ATTR(hid1, 0600, show_hid1, store_hid1),
 675         __ATTR(hid4, 0600, show_hid4, store_hid4),
 676         __ATTR(hid5, 0600, show_hid5, store_hid5),
 677         __ATTR(ima0, 0600, show_ima0, store_ima0),
 678         __ATTR(ima1, 0600, show_ima1, store_ima1),
 679         __ATTR(ima2, 0600, show_ima2, store_ima2),
 680         __ATTR(ima3, 0600, show_ima3, store_ima3),
 681         __ATTR(ima4, 0600, show_ima4, store_ima4),
 682         __ATTR(ima5, 0600, show_ima5, store_ima5),
 683         __ATTR(ima6, 0600, show_ima6, store_ima6),
 684         __ATTR(ima7, 0600, show_ima7, store_ima7),
 685         __ATTR(ima8, 0600, show_ima8, store_ima8),
 686         __ATTR(ima9, 0600, show_ima9, store_ima9),
 687         __ATTR(imaat, 0600, show_imaat, store_imaat),
 688         __ATTR(btcr, 0600, show_btcr, store_btcr),
 689         __ATTR(pccr, 0600, show_pccr, store_pccr),
 690         __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
 691         __ATTR(der, 0600, show_der, store_der),
 692         __ATTR(mer, 0600, show_mer, store_mer),
 693         __ATTR(ber, 0600, show_ber, store_ber),
 694         __ATTR(ier, 0600, show_ier, store_ier),
 695         __ATTR(sier, 0600, show_sier, store_sier),
 696         __ATTR(siar, 0600, show_siar, store_siar),
 697         __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
 698         __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
 699         __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
 700         __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
 701 #endif /* CONFIG_DEBUG_KERNEL */
 702 };
 703 #endif /* HAS_PPC_PMC_PA6T */
 704 #endif /* HAS_PPC_PMC_CLASSIC */
 705
 706 static void register_cpu_online(unsigned int cpu)
 707 {
 708         struct cpu *c = &per_cpu(cpu_devices, cpu);
 709         struct device *s = &c->dev;
 710         struct device_attribute *attrs, *pmc_attrs;
 711         int i, nattrs;
 712
 713 #ifdef CONFIG_PPC64
 714         if (cpu_has_feature(CPU_FTR_SMT))
 715                 device_create_file(s, &dev_attr_smt_snooze_delay);
 716 #endif
 717
 718         /* PMC stuff */
 719         switch (cur_cpu_spec->pmc_type) {
 720 #ifdef HAS_PPC_PMC_IBM
 721         case PPC_PMC_IBM:
 722                 attrs = ibm_common_attrs;
 723                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 724                 pmc_attrs = classic_pmc_attrs;
 725                 break;
 726 #endif /* HAS_PPC_PMC_IBM */
 727 #ifdef HAS_PPC_PMC_G4
 728         case PPC_PMC_G4:
 729                 attrs = g4_common_attrs;
 730                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 731                 pmc_attrs = classic_pmc_attrs;
 732                 break;
 733 #endif /* HAS_PPC_PMC_G4 */
 734 #ifdef HAS_PPC_PMC_PA6T
 735         case PPC_PMC_PA6T:
 736                 /* PA Semi starts counting at PMC0 */
 737                 attrs = pa6t_attrs;
 738                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 739                 pmc_attrs = NULL;
 740                 break;
 741 #endif /* HAS_PPC_PMC_PA6T */
 742         default:
 743                 attrs = NULL;
 744                 nattrs = 0;
 745                 pmc_attrs = NULL;
 746         }
 747
 748         for (i = 0; i < nattrs; i++)
 749                 device_create_file(s, &attrs[i]);
 750
 751         if (pmc_attrs)
 752                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 753                         device_create_file(s, &pmc_attrs[i]);
 754
 755 #ifdef CONFIG_PPC64
 756         if (cpu_has_feature(CPU_FTR_MMCRA))
 757                 device_create_file(s, &dev_attr_mmcra);
 758
 759         if (cpu_has_feature(CPU_FTR_PURR)) {
 760                 if (!firmware_has_feature(FW_FEATURE_LPAR))
 761                         add_write_permission_dev_attr(&dev_attr_purr);
 762                 device_create_file(s, &dev_attr_purr);
 763         }
 764
 765         if (cpu_has_feature(CPU_FTR_SPURR))
 766                 device_create_file(s, &dev_attr_spurr);
 767
 768         if (cpu_has_feature(CPU_FTR_DSCR))
 769                 device_create_file(s, &dev_attr_dscr);
 770
 771         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 772                 device_create_file(s, &dev_attr_pir);
 773 #endif /* CONFIG_PPC64 */
 774
 775 #ifdef CONFIG_PPC_FSL_BOOK3E
 776         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 777                 device_create_file(s, &dev_attr_pw20_state);
 778                 device_create_file(s, &dev_attr_pw20_wait_time);
 779
 780                 device_create_file(s, &dev_attr_altivec_idle);
 781                 device_create_file(s, &dev_attr_altivec_idle_wait_time);
 782         }
 783 #endif
 784         cacheinfo_cpu_online(cpu);
 785 }
 786
 787 #ifdef CONFIG_HOTPLUG_CPU
 788 static void unregister_cpu_online(unsigned int cpu)
 789 {
 790         struct cpu *c = &per_cpu(cpu_devices, cpu);
 791         struct device *s = &c->dev;
 792         struct device_attribute *attrs, *pmc_attrs;
 793         int i, nattrs;
 794
 795         BUG_ON(!c->hotpluggable);
 796
 797 #ifdef CONFIG_PPC64
 798         if (cpu_has_feature(CPU_FTR_SMT))
 799                 device_remove_file(s, &dev_attr_smt_snooze_delay);
 800 #endif
 801
 802         /* PMC stuff */
 803         switch (cur_cpu_spec->pmc_type) {
 804 #ifdef HAS_PPC_PMC_IBM
 805         case PPC_PMC_IBM:
 806                 attrs = ibm_common_attrs;
 807                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 808                 pmc_attrs = classic_pmc_attrs;
 809                 break;
 810 #endif /* HAS_PPC_PMC_IBM */
 811 #ifdef HAS_PPC_PMC_G4
 812         case PPC_PMC_G4:
 813                 attrs = g4_common_attrs;
 814                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 815                 pmc_attrs = classic_pmc_attrs;
 816                 break;
 817 #endif /* HAS_PPC_PMC_G4 */
 818 #ifdef HAS_PPC_PMC_PA6T
 819         case PPC_PMC_PA6T:
 820                 /* PA Semi starts counting at PMC0 */
 821                 attrs = pa6t_attrs;
 822                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 823                 pmc_attrs = NULL;
 824                 break;
 825 #endif /* HAS_PPC_PMC_PA6T */
 826         default:
 827                 attrs = NULL;
 828                 nattrs = 0;
 829                 pmc_attrs = NULL;
 830         }
 831
 832         for (i = 0; i < nattrs; i++)
 833                 device_remove_file(s, &attrs[i]);
 834
 835         if (pmc_attrs)
 836                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 837                         device_remove_file(s, &pmc_attrs[i]);
 838
 839 #ifdef CONFIG_PPC64
 840         if (cpu_has_feature(CPU_FTR_MMCRA))
 841                 device_remove_file(s, &dev_attr_mmcra);
 842
 843         if (cpu_has_feature(CPU_FTR_PURR))
 844                 device_remove_file(s, &dev_attr_purr);
 845
 846         if (cpu_has_feature(CPU_FTR_SPURR))
 847                 device_remove_file(s, &dev_attr_spurr);
 848
 849         if (cpu_has_feature(CPU_FTR_DSCR))
 850                 device_remove_file(s, &dev_attr_dscr);
 851
 852         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 853                 device_remove_file(s, &dev_attr_pir);
 854 #endif /* CONFIG_PPC64 */
 855
 856 #ifdef CONFIG_PPC_FSL_BOOK3E
 857         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 858                 device_remove_file(s, &dev_attr_pw20_state);
 859                 device_remove_file(s, &dev_attr_pw20_wait_time);
 860
 861                 device_remove_file(s, &dev_attr_altivec_idle);
 862                 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
 863         }
 864 #endif
 865         cacheinfo_cpu_offline(cpu);
 866 }
 867
 868 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
 869 ssize_t arch_cpu_probe(const char *buf, size_t count)
 870 {
 871         if (ppc_md.cpu_probe)
 872                 return ppc_md.cpu_probe(buf, count);
 873
 874         return -EINVAL;
 875 }
 876
 877 ssize_t arch_cpu_release(const char *buf, size_t count)
 878 {
 879         if (ppc_md.cpu_release)
 880                 return ppc_md.cpu_release(buf, count);
 881
 882         return -EINVAL;
 883 }
 884 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
 885
 886 #endif /* CONFIG_HOTPLUG_CPU */
 887
 888 static int sysfs_cpu_notify(struct notifier_block *self,
 889                                       unsigned long action, void *hcpu)
 890 {
 891         unsigned int cpu = (unsigned int)(long)hcpu;
 892
 893         switch (action) {
 894         case CPU_ONLINE:
 895         case CPU_ONLINE_FROZEN:
 896                 register_cpu_online(cpu);
 897                 break;
 898 #ifdef CONFIG_HOTPLUG_CPU
 899         case CPU_DEAD:
 900         case CPU_DEAD_FROZEN:
 901                 unregister_cpu_online(cpu);
 902                 break;
 903 #endif
 904         }
 905         return NOTIFY_OK;
 906 }
 907
 908 static struct notifier_block sysfs_cpu_nb = {
 909         .notifier_call  = sysfs_cpu_notify,
 910 };
 911
 912 static DEFINE_MUTEX(cpu_mutex);
 913
 914 int cpu_add_dev_attr(struct device_attribute *attr)
 915 {
 916         int cpu;
 917
 918         mutex_lock(&cpu_mutex);
 919
 920         for_each_possible_cpu(cpu) {
 921                 device_create_file(get_cpu_device(cpu), attr);
 922         }
 923
 924         mutex_unlock(&cpu_mutex);
 925         return 0;
 926 }
 927 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
 928
 929 int cpu_add_dev_attr_group(struct attribute_group *attrs)
 930 {
 931         int cpu;
 932         struct device *dev;
 933         int ret;
 934
 935         mutex_lock(&cpu_mutex);
 936
 937         for_each_possible_cpu(cpu) {
 938                 dev = get_cpu_device(cpu);
 939                 ret = sysfs_create_group(&dev->kobj, attrs);
 940                 WARN_ON(ret != 0);
 941         }
 942
 943         mutex_unlock(&cpu_mutex);
 944         return 0;
 945 }
 946 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
 947
 948
 949 void cpu_remove_dev_attr(struct device_attribute *attr)
 950 {
 951         int cpu;
 952
 953         mutex_lock(&cpu_mutex);
 954
 955         for_each_possible_cpu(cpu) {
 956                 device_remove_file(get_cpu_device(cpu), attr);
 957         }
 958
 959         mutex_unlock(&cpu_mutex);
 960 }
 961 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
 962
 963 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
 964 {
 965         int cpu;
 966         struct device *dev;
 967
 968         mutex_lock(&cpu_mutex);
 969
 970         for_each_possible_cpu(cpu) {
 971                 dev = get_cpu_device(cpu);
 972                 sysfs_remove_group(&dev->kobj, attrs);
 973         }
 974
 975         mutex_unlock(&cpu_mutex);
 976 }
 977 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
 978
 979
 980 /* NUMA stuff */
 981
 982 #ifdef CONFIG_NUMA
 983 static void register_nodes(void)
 984 {
 985         int i;
 986
 987         for (i = 0; i < MAX_NUMNODES; i++)
 988                 register_one_node(i);
 989 }
 990
 991 int sysfs_add_device_to_node(struct device *dev, int nid)
 992 {
 993         struct node *node = node_devices[nid];
 994         return sysfs_create_link(&node->dev.kobj, &dev->kobj,
 995                         kobject_name(&dev->kobj));
 996 }
 997 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
 998
 999 void sysfs_remove_device_from_node(struct device *dev, int nid)
1000 {
1001         struct node *node = node_devices[nid];
1002         sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1003 }
1004 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1005
1006 #else
1007 static void register_nodes(void)
1008 {
1009         return;
1010 }
1011
1012 #endif
1013
1014 /* Only valid if CPU is present. */
1015 static ssize_t show_physical_id(struct device *dev,
1016                                 struct device_attribute *attr, char *buf)
1017 {
1018         struct cpu *cpu = container_of(dev, struct cpu, dev);
1019
1020         return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1021 }
1022 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1023
1024 static int __init topology_init(void)
1025 {
1026         int cpu;
1027
1028         register_nodes();
1029
1030         cpu_notifier_register_begin();
1031
1032         for_each_possible_cpu(cpu) {
1033                 struct cpu *c = &per_cpu(cpu_devices, cpu);
1034
1035                 /*
1036                  * For now, we just see if the system supports making
1037                  * the RTAS calls for CPU hotplug.  But, there may be a
1038                  * more comprehensive way to do this for an individual
1039                  * CPU.  For instance, the boot cpu might never be valid
1040                  * for hotplugging.
1041                  */
1042                 if (ppc_md.cpu_die)
1043                         c->hotpluggable = 1;
1044
1045                 if (cpu_online(cpu) || c->hotpluggable) {
1046                         register_cpu(c, cpu);
1047
1048                         device_create_file(&c->dev, &dev_attr_physical_id);
1049                 }
1050
1051                 if (cpu_online(cpu))
1052                         register_cpu_online(cpu);
1053         }
1054
1055         __register_cpu_notifier(&sysfs_cpu_nb);
1056
1057         cpu_notifier_register_done();
1058
1059 #ifdef CONFIG_PPC64
1060         sysfs_create_dscr_default();
1061 #endif /* CONFIG_PPC64 */
1062
1063         return 0;
1064 }
1065 subsys_initcall(topology_init);